Placing and routing debugging logic
AssigneeSynopsys, Inc.
InventorLudovic Marc Larzul
Life of this patent
Estimating the term…
Abstract
Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more emulator FPGAs, the host system places debugging logic units of the debugging logic evenly across the FPGA before placing logic components of the DUT.
Claims16
A non-transitory computer readable medium storing instructions, the instructions when executed by one or more processors cause the one or more processors to:
- determine placement of a plurality of logic components included in a design under test (DUT) on an emulation hardware component;
- identify at least one logic component of the plurality of the logic components having an output signal to be traced during an emulation;
- determine placement of a debugging logic unit on the emulation hardware component based on the placement of the at least one logic component having a signal to be traced;
- responsive to the determination of the placement of the plurality of logic components and the determination of the placement of the debugging logic unit:
- determine routing of a connection between the debugging logic unit and the at least one logic component having a signal to be traced, and
- determine routings among the plurality of logic components;
- and
- transmit, to an emulator, data to configure the emulation hardware component included in the emulator based on the determined placements and the determined routings.
A non-transitory computer readable medium storing instructions, the instructions when executed by one or more processors cause the one or more processors to:
- determine placement of a plurality of logic components included in a design under test (DUT) on an emulation hardware component;
- determine routings among the plurality of logic components;
- responsive to the determination of the routings among the plurality of logic components:
- determine placement of a debugging logic unit on the emulation hardware component based on the placement of at least one logic component of the plurality of logic components having a signal to be traced, and
- determine routing of a connection between the debugging logic unit and the at least one logic component having a signal to be traced;
- and
- transmit, to an emulator, data to configure the emulation hardware component included in the emulator based on the determined placements and the determined routings.
Dependencies are inferred from the claim text.