US 9,959,380 B2Granted

Integrated circuit design systems and methods

AssigneeMotivo, Inc.

InventorsVito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan

Life of this patent

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Abstract

Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.

Claims20

Dependent claims

A method, performed by one or more processors, for determining a physical layout pattern for an integrated circuit electrical design, the method comprising:

accessing a layout pattern configuration graph comprising a plurality of layout pattern configurations, wherein at least two of the plurality of layout pattern configurations of the layout pattern configuration graph are annotated with characteristics representing physical layout geometry;
partitioning the integrated circuit electrical design into a plurality of circuit design configurations including one specific circuit design configuration;
and
selecting, based on the annotated characteristics of the physical layout geometry, one of the at least two of the plurality of layout pattern configurations from the layout pattern configuration graph, the selected one of the at least two of the plurality of layout configurations corresponding to the one specific circuit design configuration of the integrated circuit electrical design;
determining a manufacturing configuration for manufacturing an integrated circuit, the manufacturing configuration comprising the physical layout pattern of the integrated circuit electrical design including the selected one of the at least two of the plurality of layout pattern configurations;
and
manufacturing the integrated circuit using the determined manufacturing configuration;
wherein the accessing comprises defining at least one of the plurality of layout pattern configurations as at least one two-dimensional grid with rows and columns, wherein grid cells of the two-dimensional grid are defined as completely filled or completely empty;
and
wherein the at least two of the plurality of layout pattern configurations of the layout pattern configuration graph are annotated with the characteristics representing the physical layout geometry by:
identifying the at least one two-dimensional grid in at least one of the at least two of the plurality of layout pattern configurations of the layout pattern configuration graph;
and
determining row-heights of the rows and column-widths of the columns of the two-dimensional grid.

10 more elements

A method, performed by one or more processors, for determining a physical layout pattern for an integrated circuit electrical design, the method comprising:

accessing a layout pattern configuration graph comprising a plurality of layout pattern configurations, wherein at least two of the plurality of layout pattern configurations of the layout pattern configuration graph are annotated with characteristics representing physical layout geometry;
partitioning the integrated circuit electrical design into a plurality of circuit design configurations including one specific circuit design configuration;
and
selecting, based on the annotated characteristics of the physical layout geometry, one of the at least two of the plurality of layout pattern configurations from the layout pattern configuration graph, the selected one of the at least two of the plurality of layout configurations corresponding to the one specific circuit design configuration of the integrated circuit electrical design;
determining a manufacturing configuration for manufacturing an integrated circuit, the manufacturing configuration comprising the physical layout pattern of the integrated circuit electrical design including the selected one of the at least two of the plurality of layout pattern configurations;
and
manufacturing the integrated circuit using the determined manufacturing configuration;
wherein the accessing comprises defining at least one of the plurality of layout pattern configurations as at least one two-dimensional grid with rows and columns, wherein grid cells of the two-dimensional grid are defined as completely filled or completely empty;
and
wherein the at least two of the plurality of layout pattern configurations of the layout pattern configuration graph are annotated with the characteristics representing the physical layout geometry by:
identifying the two-dimensional grid in at least one of the at least two of the plurality of layout pattern configurations of the layout pattern configuration graph;
and
computing one or more geometric properties from the identified two-dimensional grid.

10 more elements

A method, performed by one or more processors, for determining a physical layout pattern for an integrated circuit electrical design, the method comprising:

accessing a layout pattern configuration graph comprising a plurality of layout pattern configurations, wherein at least two of the plurality of layout pattern configurations of the layout pattern configuration graph are annotated with characteristics;
partitioning the integrated circuit electrical design into a plurality of circuit design configurations including one specific circuit design configuration;
and
selecting, based on the annotated characteristics of the physical layout geometry, one of the at least two of the plurality of layout pattern configurations from the layout pattern configuration graph, the selected one of the at least two of the plurality of layout configurations corresponding to the one specific circuit design configuration of the integrated circuit electrical design;
and
determining a manufacturing configuration for manufacturing an integrated circuit, the manufacturing configuration comprising the physical layout pattern of the integrated circuit electrical design including the selected one of the at least two of the plurality of layout pattern configurations;
and
manufacturing the integrated circuit using the determined manufacturing configuration;
wherein the accessing comprises defining at least one of the plurality of layout pattern configurations as at least one two-dimensional grid with rows and columns, wherein grid cells of the two-dimensional grid are defined as completely filled or completely empty;
and
wherein the at least two of the plurality of layout pattern configurations of the layout pattern configuration graph are annotated with the characteristics representing physical layout geometry by:
identifying the at least one two-dimensional grid in at least one of the at least two of the plurality of layout pattern configurations of the layout pattern configuration graph;
and determining row-heights of the rows and column-widths of the columns of the two-dimensional grid.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/343,536Filed 4 Nov 2016 · us provisional application
Priority: 28 Mar 2016
Published: US 2017/0277818 A128 Sep 2017
Granted: 1 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/18
Geometric CAD: network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air…
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking