Hybrid compilation for FPGA prototyping
AssigneeMentor Graphics Corporation
InventorsSanjay Gupta, Praveen Shukla
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.
Claims24
One or more computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
- generating, based on an original RTL (register-transfer level) design for a circuit design, an initial FPGA-mapped netlist and a generic RTL design, the generic RTL design being functionally equivalent to the initial FPGA-mapped netlist and maintaining one-to-one correspondence to the initial FPGA-mapped netlist in terms of design hierarchy for at least a part of the circuit design;
- partitioning, based on the initial FPGA-mapped netlist, the circuit design into design partitions for implementing the circuit design across a plurality of FPGA chips, each of the design partitions corresponding to a partition of the generic RTL design and to a partition of the initial FPGA-mapped netlist;
- and
- generating final FPGA-mapped netlists based on the design partitions, wherein the design partitions are represented by the partitions of the generic RTL design, or some of the design partitions are represented by the partitions of the generic RTL design and each of the rest of the design partitions is represented by a combination of the generic RTL design and the initial FPGA-mapped netlist.
A method, executed by at least one processor of a computer, comprising:
- generating, based on an original RTL (register-transfer level) design for a circuit design, an initial FPGA-mapped netlist and a generic RTL design, the generic RTL design being functionally equivalent to the initial FPGA-mapped netlist and maintaining one-to-one correspondence to the initial FPGA-mapped netlist in terms of design hierarchy for at least a part of the circuit design;
- partitioning, based on the initial FPGA-mapped netlist, the circuit design into design partitions for implementing the circuit design across a plurality of FPGA chips, each of the design partitions corresponding to a partition of the generic RTL design and to a partition of the initial FPGA-mapped netlist;
- and
- generating final FPGA-mapped netlists based on the design partitions, wherein the design partitions are represented by the partitions of the generic RTL design, or some of the design partitions are represented by the partitions of the generic RTL design and each of the rest of the design partitions is represented by a combination of the generic RTL design and the initial FPGA-mapped netlist.
A system comprising:
- one or more processors, the one or more processors programmed to perform a method, the method comprising:
- generating, based on an original RTL(register-transfer level) design for a circuit design, an initial FPGA-mapped netlist and a generic RTL design, the generic RTL design being functionally equivalent to the initial FPGA-mapped netlist and maintaining one-to-one correspondence to the initial FPGA-mapped netlist in terms of design hierarchy for at least a part of the circuit design;
- partitioning, based on the initial FPGA-mapped netlist, the circuit design into design partitions for implementing the circuit design across a plurality of FPGA chips, each of the design partitions corresponding to a partition of the generic RTL design and to a partition of the initial FPGA-mapped netlist;
- and
- generating final FPGA-mapped netlists based on the design partitions, wherein the design partitions are represented by the partitions of the generic RTL design, or some of the design partitions are represented by the partitions of the generic RTL design and each of the rest of the design partitions is represented by a combination of the generic RTL design and the initial FPGA-mapped netlist.
Dependencies are inferred from the claim text.