US 9,959,377 B2 · Iterative solution using compressed inductive matrix for efficient simulation of very-large scale circuits

Abstract

Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is obtained and parsed, where the netlist describes the circuit having one or more branches and one or more nodes. A linear system describing the circuit is obtained and compressed using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a dense matrix in a low-rank format to reduce the density of the matrix. The linear system is then solved using an iterative operation. An initial guess is used for the voltage at each node and the current through each branch. After performing the first iteration, an initial estimate for the voltage and current is stored and used as the initial guess for the second iteration. The iterative operation is continued until the estimate for the voltage at each node and the current through each branch is sufficiently accurate.

Claims14

Dependent claims

A circuit analysis method for use in the design of an integrated circuit, the circuit analysis method comprising:

obtaining a netlist of a circuit, the circuit containing one or more nodes and one or more branches;
generating from the netlist a linear system describing the circuit, the linear system comprising a mathematical representation of the circuit that is defined as {tilde over (G)}x+s{tilde over (C)}x=e, where
G
~
=
[
G
n
A
rl
T
-
A
rl
0
]
,
C
~
=
[
C
n
0
0
L
]
,
Gn is a matrix of node conductances, Cn is a matrix of node capacitances, Arl is the incidence matrix describing the circuit, L is a matrix of self and mutual branch inductances, x is a matrix of node voltages and branch currents, and e is a matrix of independent current source excitations;
compressing the linear system using a hierarchical approach to reduce a complexity of the linear system;
using an iterative operation, solving the compressed linear system to obtain a voltage at each of the one or more nodes and a current through each of the one or more branches, said obtained voltages and currents being usable in said design of the integrated circuit.

28 more elements

A non-transitory program storage device readable by a machine, embodying a program of instructions executable by the machine to perform a circuit analysis method for use in the design of an integrated circuit, the circuit analysis method comprising:

obtaining a netlist of a circuit, the circuit containing one or more nodes and one or more branches;
generating from the netlist a linear system describing the circuit, the linear system comprising a mathematical representation of the circuit that is defined as {tilde over (G)}x+s{tilde over (C)}x=e, where
G
~
=
[
G
n
A
rl
T
-
A
rl
0
]
,
C
~
=
[
C
n
0
0
L
]
,
Gn is a matrix of node conductances, Cn is a matrix of node capacitances, Arl is the incidence matrix describing the circuit, L is a matrix of self and mutual branch inductances, x is a matrix of node voltages and branch currents, and e is a matrix of independent current source excitations;
compressing the linear system using a hierarchical approach to reduce a complexity of the linear system;
using an iterative operation, solving the compressed linear system to obtain a voltage at each of the one or more nodes and a current through each of the one or more branches, said obtained voltages and currents being usable in said design of the integrated circuit.

28 more elements

Dependencies are inferred from the claim text.

Iterative solution using compressed inductive matrix for efficient simulation of very-large scale circuits

Life of this patent

Iterative solution using compressed inductive matrix for efficient simulation of very-large scale circuits

Life of this patent

Abstract

Claims14