Efficient emulation and logic analysis
AssigneeSynopsys, Inc.
InventorLudovic Marc Larzul
Life of this patent
Estimating the term…
Abstract
An emulation environment includes a host system and an emulator. The host system configures the emulator to load a design under test (DUT) and the emulator emulates the DUT. The emulator includes one or more design field-programmable gate arrays (FPGAs) that emulate the DUT. In addition, the emulator includes at least one system FPGA with a logic analyzer and multiple virtual FPGA. The virtual FPGAs emulate sections of the DUT. By the virtual FPGAs emulating sections of the DUT, the logic analyzer is able to obtain for performing logic analysis certain signals from the virtual FPGAs, rather than from the design FPGAs.
Claims20
An emulator comprising:
- a plurality of design field-programmable gate arrays (FPGAs) configured to collectively emulate a design under test (DUT) and produce a first signal of the DUT, wherein a first design FPGA of the plurality of design FPGAs is configured to emulate a section of the DUT;
- and
- a system FPGA in communication with the plurality of design FPGAs and configured to receive the first signal from the first design FPGA, the system FPGA comprising:
- a plurality of virtual FPGAs, at least one of the plurality of virtual FPGAs configured to receive the first signal, emulate substantially the same section of the DUT that the first design FPGA is configured to emulate, and produce a second signal of the DUT based on the first signal, and
- a logic analyzer configured to perform logic analysis based on the second signal.
A non-transitory computer readable medium storing instructions, the instructions to configure an emulator to:
- emulate, with a design field-programmable gate array (FPGA), a section of a design under test (DUT);
- produce, by the design FPGA, a first signal based on the emulation of the section;
- transmit, from the design FPGA to a system FPGA, the first signal produced by the design FPGA;
- emulate, with a virtual FPGA within the system FPGA, substantially the same section of the DUT that was emulated with the design FPGA, the emulation with the virtual FPGA based on the first signal;
- produce, by the virtual FPGA, a second signal based on the emulation of the substantially the same section;
- and
- perform logic analysis based on the second signal.
A method comprising:
- emulating, with a design field-programmable gate array (FPGA), a section of a design under test (DUT);
- producing, by the design FPGA, a first signal based on the emulation of the section;
- transmitting, from the design FPGA to a system FPGA, the first signal produced by the design FPGA;
- emulating, with a virtual FPGA within the system FPGA, substantially the same section of the DUT that was emulated with the design FPGA, the emulation with the virtual FPGA based on the first signal;
- producing, by the virtual FPGA, a second signal based on the emulation of the substantially the same section;
- and
- performing logic analysis based on the second signal.
A non-transitory computer readable medium configured to store instructions, the instructions executed by one or more processors for:
- transmitting, by a host system to an emulator, information to configure a plurality of design field-programmable gate arrays (FPGAs) included in the emulator to collectively emulate a design under test (DUT);
- identifying, by the host system, a plurality of signals of the DUT used by a system FPGA included in the emulator in performing logic analysis during emulation of the DUT, the system FPGA in communication with each of the plurality of design FPGAs for receiving a subset of the identified plurality of signals from the design FPGAs;
- selecting, by the host system from a plurality of computational blocks included in the system FPGA, a subset of computational blocks to configure for the emulation of the DUT, the subset of computational blocks selected based on the identified plurality of signals and selected to emulate at least a section of the DUT that is substantially the same as a section emulated by one of the plurality of design FPGAs;
- and
- transmitting, by the host system to the emulator, information to configure the computational blocks in the subset for the emulation, at least one of the computational blocks in the subset configured based on the information to generate a signal from the plurality of signals during the emulation.
Dependencies are inferred from the claim text.