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US 9,959,236 B2Granted
Observing an internal link via an existing port for system on chip devices
AssigneeIntel Corporation
InventorSyed Z. Islam
Life of this patent
Estimating the term…
Abstract
Methods and apparatus relating to observing an internal link via an existing port for System On Chip (SOC) devices are described. In one embodiment, a logic within an SOC device may allow an external logic analyzer to observe communication between a first and second component of the SOC through an existing (e.g., shared and/or non-dedicated) interface. Other embodiments are also disclosed.
Claims20
A System On Chip (SOC) device comprising:
- a first component;
- a second component coupled to the first component via an internal link, wherein the first and second components are to communicate via the internal link without use of any analog communication logic;
- and
- logic to enable communication between the SOC device and an external link coupled to the SOC device, wherein the logic is to comprise a test controller to cause monitoring of operations of one or more components of the SOC device or cause monitoring of communications between the one or more components of the SOC device in response to a signal, wherein the test controller is to cause selection of input signals of a first selection logic and a second selection logic based at least in part on one or more bits stored in one or more configuration registers, wherein the first selection logic is to receive input from the internal link, wherein the second selection logic is to receive input from the first selection logic and the external link.
1 more element
A method comprising:
- establishing communication between a first component and a second component via an internal link and without use of any analog communication logic;
- and
- enabling communication between a SOC device, which comprises the first and second component, and an external link coupled to the SOC device;
- causing monitoring of operations of one or more components of the SOC device or causing monitoring of communications between the one or more components of the SOC device in response to a signal;
- and
- causing selection of input signals of a first selection logic and a second selection logic based at least in part on one or more bits stored in one or more configuration registers, wherein the first selection logic receives input from the internal link, wherein the second selection logic receives input from the first selection logic and the external link.
3 more elements
A system comprising:
- a plurality of synchronization buffers to transfer data between a first clock domain and a second clock domain;
- a first component;
- a second component coupled to the first component via an internal link, wherein the first and second components are to communicate via the internal link without use of any analog communication logic;
- and
- logic to enable communication between the SOC device and an external link coupled to the SOC device, wherein the logic is to comprise a test controller to cause monitoring of operations of one or more components of the SOC device or cause monitoring of communications between the one or more components of the SOC device in response to a signal, wherein the test controller is to cause selection of input signals of a first selection logic and a second selection logic based at least in part on one or more bits stored in one or more configuration registers, wherein the first selection logic is to receive input from the internal link, wherein the second selection logic is to receive input from the first selection logic and the external link.
2 more elements
Dependencies are inferred from the claim text.