Reducing input/output latency using a direct memory access (DMA) engine

A computer-readable storage medium including instructions that upon execution cause a computer system to:

• generate a direct memory access (DMA) descriptor read command for descriptor information associated with data stored in a memory buffer;
• in response to the DMA descriptor read command, communicate the descriptor information to a first parsing engine in a DMA engine for parsing;
• detect the descriptor information by a second parsing engine, while the descriptor information is communicated to the first parsing engine;
• and
• prefetch, using the second parsing engine, the data from the memory buffer to cache, based on the detected descriptor information, wherein a physical distance between the second parsing engine and the cache is less than a physical distance between the first parsing engine and the cache.

A system, comprising:

• a direct memory access (DMA) engine with a first parser;
• and
• a memory subsystem, comprising:
• a processor;
• memory configured to store data;
• cache that is separate from the memory;
• and
• a second parser, the second parser being outside of the DMA engine and disposed such that the second parser has a shorter information pathway to the cache than an information pathway between the DMA engine and the cache;
• wherein the processor is configured to:
• store descriptor information in the cache, the descriptor information associated with the data;
• signal the second parser to prefetch the data;
• responsive to setting the register bit, receive a DMA descriptor read command for the descriptor information;
• detect a prefetch enable indicator associated with the DMA descriptor read command;
• and
• responsive to detecting the prefetch enable indicator, communicate the descriptor information to the first parser and the second parser.