Device generated interrupts compatible with limited interrupt virtualization hardware

A peripheral component interconnect express (PCIe) device for generating interrupts in a computer system using limited interrupt virtualization hardware, comprising:

• a memory storing instructions;
• a processor in communication with the memory, the processor executing the instructions to:
• atomically set one or more bits in a posted interrupt vector (PIV) of a target central processing unit (CPU), wherein atomically setting the one or more bits comprises at least one of:
• executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2(b modulo 32), where b is a bit in the PIV,
• using PCIe byte enables to write to a single byte in a PCIe address space that contains the one or more bits without modifying neighboring bytes in the PCIe address space, or
• performing a PCIe swap to the PIV by writing a bitvector setting a single vector, and
• send an interrupt to the target CPU, the interrupt notifying the target CPU of changes to the PIV.

A non-transitory computer readable medium storing instructions executable by a processor to perform a method generating interrupts in a computer system using limited interrupt virtualization hardware, the method comprising:

• atomically setting one or more bits in a posted interrupt vector (PIV) of a target central processing unit (CPU), wherein atomically setting the one or more bits comprises at least one of:
• executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2(b modulo 32), where b is a bit in the PIV,
• using peripheral component interconnect express (PCIe) byte enables to write to a single byte in a PCIe address space that contains the one or more bits without modifying neighboring bytes in the PCIe address space, or
• performing a PCIe swap to the PIV by writing a bitvector setting a single vector, and
• sending an interrupt to the target CPU, the interrupt notifying the target CPU of changes to the PIV.

A system, comprising:

• a peripheral component interconnect express (PCIe) device;
• at least one central processing unit (CPU) core, the at least one CPU core including a target CPU core;
• and
• a Virtualization Technology for Directed I/O (VT-d) coupled to the PCIe device through a PCIe switch and in communication with the at least one CPU core, the VT-d enabling communication between the PCIe device and the at least one CPU core,
• wherein the PCIe device is programmed to atomically set one or more bits in a posted interrupt vector (PIV) of the target CPU, and send an interrupt to the target CPU through the VT-d, the interrupt notifying a target CPU of changes to the PIV, and
• wherein atomically setting one or more bits in the PIV comprises at least one of:
• executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2(b modulo 32), where b is a bit in the PIV,
• using PCIe byte enables to write to a single byte in a PCIe address space that contains the one or more bits without modifying neighboring bytes in the PCIe address space, or
• performing a PCIe swap to the PIV by writing a bitvector setting a single vector.