Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
AssigneeInternational Business Machines Corporation
InventorsGuy L. Guthrie, Hugh Shen, Derek E. Williams
Life of this patent
Estimating the term…
Abstract
A technique for operating a lower level cache memory of a data processing system includes receiving, by a store queue controller, an operation that is associated with a first thread. The store queue controller uses level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.
Claims11
A method of operating a lower level cache memory of a data processing system, comprising:
- receiving, by a store queue controller, an operation that is associated with a first thread;
- and
- using, by the store queue controller, level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary, wherein the operation is a synchronization operation and the using further comprises:
- setting, by the store queue controller, dependencies in the dependency data structure of the store queue of the lower level cache memory for the synchronization operation to store operations not on the first thread that hit in the L1 cache memory.
A lower level cache memory, comprising:
- a data array;
- a store queue coupled to the data array and configured to buffer synchronization operations and store operations;
- and
- a store queue controller coupled to the store queue and configured to:
- receive an operation that is associated with a first thread;
- and
- use level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of the store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary, wherein the operation is a store operation and the store queue controller is further configured to:
- set dependencies in the dependency data structure of the store queue of the lower level cache memory for the store operation to synchronization/barrier operations on the first thread.
A data processing system, comprising:
- a processor core;
- and
- a lower level cache memory coupled to the processor core, wherein the lower level cache memory includes:
- a data array;
- a store queue coupled to the data array and configured to buffer synchronization operations and store operations;
- a store queue controller coupled to the store queue and configured to:
- receive an operation that is associated with a first thread;
- and
- use level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of the store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary, wherein the operation is one of a synchronization operation and a store operation, and wherein when the operation is the synchronization operation the store queue controller is further configured to:
- set dependencies in the dependency data structure of the store queue of the lower level cache memory for the synchronization operation to store operations not on the first thread that hit in the L1 cache memory.
Dependencies are inferred from the claim text.