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US 9,959,212 B2Granted
Memory system
AssigneeKabushiki Kaisha Toshiba
InventorSusumu Takeda
Life of this patent
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Abstract
A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.
Claims20
A memory system comprising:
- a first cache memory comprising a volatile memory;
- a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory;
- and
- a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.
1 more element
A memory system comprising:
- a first cache memory comprising a volatile memory that does not require error correction processing during reading;
- a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, the non-volatile memory requiring error correction processing during reading;
- a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer;
- and
- an error correction circuitry to carry out the error correction processing on data read from the second cache memory.
2 more elements
Dependencies are inferred from the claim text.