Parallel caching architecture and methods for block-based data processing

A multi-processor computer system with shared memory resources, the computer system comprising:

• a first plurality of sensors configured to acquire inertial and positional data related to a mobile platform;
• a first plurality of co-processors communicatively coupled to the first plurality of sensors, the first plurality of co-processors including a hardware logic configured to control the acquisition of the inertial and positional data and configured to analyze the acquired inertial and positional data;
• a second plurality of sensors configured to acquire input data related to the mobile platform;
• a second plurality of co-processors communicatively coupled to the second plurality of sensors, the second plurality of co-processors including a hardware logic configured to receive a plurality of streams of input data from the second plurality of sensors and configured to segment the input data into a plurality of discrete data segments, wherein each data segment includes an element of input data stream and a subset of the inertial and positional data related to the element of input data stream, wherein the data segment comprises a stride and wherein each stride comprises an element of the input data and a subset of the inertial and positional data related to the element of input data stream;
• at least one array of Double Data Rate (DDR) memory blocks and a memory controller communicatively coupled to the at least one array of DDR memory blocks and the plurality of hardware processing units, the memory controller configured to store and retrieve the plurality of strides in/from the at least one array of DDR memory blocks;
• and
• a plurality of hardware processing units configured to perform calculations related to the input data using the plurality of data segments.