Memory system and method of controlling cache memory

A memory system comprising:

• first and second memories;
• and
• a controller configured to:
• switch between first and second modes,
• search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and
• read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode, wherein
• the first memory is a cache memory,
• the first mode is a cache valid mode,
• the second mode is a cache invalid mode,
• the controller switches from the first mode to the second mode when the number of times that the read command is sequentially received from a host reaches a first predetermined number,
• the controller switches from the second mode to the first mode when a command other than the read command is received from the host, and
• the controller inhibits switching from the first mode to the second mode when the number of times that the switching from the first mode to the second mode reaches a second predetermined number.