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US 9,959,205 B2Granted
Shared row buffer system for asymmetric memory
AssigneeWisconsin Alumni Research Foundation
InventorsHao Wang, Nam Sung Kim
Life of this patent
Estimating the term…
Abstract
An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.
Claims20
An electronic memory comprising:
- a first memory bank storing data in logical first rows to be accessible through at least one row buffer;
- a second memory bank storing data in logical second rows to be accessible through at least one row buffer wherein the first memory bank has a higher data capacity and larger access latency than the second memory bank;
- a set of at least two row buffers;
- and
- a set of electrically operable switches between each row buffer and the first memory bank and second memory bank, the electrically operable switches configured so that a given row buffer can exchange data with the first memory bank or in the alternative with the second memory bank according to activation of the electrically operable switches so that each row buffer may transfer data within the electronic memory between the first memory bank and the second memory bank.
2 more elements
Dependencies are inferred from the claim text.