Node, arithmetic processing device, and arithmetic processing method

An arithmetic processing device comprising:

• a processor core configured to output a request to issue a first request to a memory provided in a first node included in a plurality of nodes in a shared memory system;
• a request issuing circuit configured to issue, based on the request from the processor core, the first request to the memory;
• a storing circuit configured to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of the plurality of nodes;
• a setting circuit configured to set, in a case where the first request has timed out, the first information for the first node in the first failure node list;
• and
• an issuance inhibition circuit configured to inhibit, when a new request to issue a second request to the memory is output from the processor core, the new request in a case where the first information is set for the first node in the first failure node list in such a manner that the second request is not issued by the request issuing circuit.

An arithmetic processing method comprising:

• storing a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of a plurality of nodes in a shared memory system;
• outputting, by a processor core in an arithmetic processing device, a request to issue a first request to a memory provided in a first node included in the plurality of nodes;
• issuing, based on the request from the processor core, the first request to the memory provided at the first node;
• setting, in a case where the first request has timed out, first information for the first node in the first failure node list;
• and
• inhibiting, when a new request to issue a second request to the memory is generated in the processor core, the new request in a case where the first information is set for the first node in the first failure node list in such a manner that the second request is not issued from the arithmetic processing device.