US 9,959,123 B2 · Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Abstract

An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

Claims7

Dependent claims

A method implemented by an information handling system that includes a memory and a processor, the method comprising:

matching a first writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in a matched one of a plurality of entries, wherein the first writeback ITAG is provided by a first one of a plurality of load store units, and wherein the entry ITAG corresponds to an instruction;
setting, in the matched entry, a first one of a plurality of ready bits that correspond to the first load store unit, wherein each of the plurality of ready bits correspond to one of the plurality of load store units;
and
issuing the instruction based upon detecting that each of the plurality of ready bits is set.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/827,284Filed 15 Aug 2015 · continuation

Priority

2 Jun 2015

Published

US 2016/0357566 A18 Dec 2016

Granted

1 May 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/3824
Concurrent instruction execution, e.g. pipeline or look ahead: operand accessing
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding

Family

Application14/728,534Parent of this continuation · filed 2 Jun 2015

US 2016/0357567 A1Pre-grant publication · published 8 Dec 2016

US 9,858,078 B2Parent of this continuation

US 2016/0357566 A1Published application

US 9,959,123 B2This patent

From the US filing history. Foreign family members aren’t listed.

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Life of this patent

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Life of this patent

Abstract

Claims7