Persistent relocatable reset vector for processor

A method comprising:

• programming a register in a logic circuit that is included in an integrated circuit and that is external to a processor in the integrated circuit with a reset vector address, wherein the programming is responsive to one or more instructions executed on the processor;
• powering down the processor subsequent to the programming, wherein the powering down the processor includes interrupting a power supply voltage to the processor;
• persisting the reset vector base address during the powering down in the register in the logic circuit;
• powering the processor up subsequent to the powering down, wherein powering up the processor includes restoring the power supply voltage to the processor;
• resetting the processor subsequent to the power up;
• the processor capturing the reset vector address from the register in the logic circuit in a reset vector base address register in the processor responsive to the resetting, wherein the logic circuit is configured to provide the reset vector address on an input to the processor;
• and
• releasing the processor from reset responsive to completing the resetting.

An integrated circuit comprising:

• one or more processors included in a first power domain of the integrated circuit, wherein each of the one or more processors includes a reset vector base address register, and wherein each of the one or more processors is configured to receive a reset vector address on an input to the processor to be captured into the reset vector base address register responsive to reset of the processor, and wherein the processor is released from reset responsive to a reset of the processor completing;
• a control circuit included in a second power domain of the integrated circuit, wherein the control circuit comprises at least one register programmable with the reset vector address for at least one of the one or more processors, wherein the at least one register is coupled to the input to the at least one of the one or more processors, and wherein the second power domain is independent of the first power domain;
• and
• a power manager circuit configured to control a power up and a power down of the first power domain, wherein the second power domain remains powered up if the integrated circuit is powered, wherein power down of the first power domain includes interrupting a power supply voltage to the first power domain and power up of the first power domain includes restoring the power supply voltage to the to the first power domain.