Computer processor employing double-ended instruction decoding

A computer processor comprising:

• an instruction buffer configured to store at least one variable-length instruction having a variable-length bit bundle bounded by a head end and a tail end with a plurality of fixed-length slots, wherein the plurality of fixed-length slots are logically partitioned into a plurality of distinct blocks with a first group of blocks extending in a logical forward order from the head end of the bit bundle toward the tail end of the bit bundle and a second group of blocks extending in a logical reverse order from the tail end of the bit bundle toward the head end of the bit bundle, wherein the second group of blocks includes a tail end block disposed adjacent the tail end of the bit bundle, wherein separate and distinct operations are encoded in the fixed-length slots of the first group of blocks and in the fixed-length slots of the second group of blocks, and wherein each variable-length instruction includes a fixed-length header separate and distinct from the variable-length bit bundle, wherein the header is located at a predefined position in the variable-length instruction and includes a first field that encodes information related to entire length of the variable-length instruction;
• and
• a decode stage, coupled to the instruction buffer, that is configured to process a given variable-length instruction stored by the instruction buffer by i) processing the header and using the information related to entire length of the variable-length instruction as encoded by the first field of the header to locate the tail end of the bit bundle and isolate and align the tail end block followed by ii) decoding at least one operation defined by the fixed-length slots of a particular block belonging to the first group of blocks in parallel with decoding at least one different operation defined by the fixed-length slots of the tail end block.