System and method for flush power aware low power mode control in a portable computing device

A computer system for a multi-core system-on-a-chip (SoC) in a portable computing device (PCD), the system comprising:

• a cache memory of the SoC;
• a low power mode controller in communication with the cache via an interconnect, the low power mode controller configured to:
• identify that the cache memory is not being accessed by any component of the SoC,
• determine for the identified non-accessed cache memory a number of dirty cache lines,
• determine for a low power mode of the cache memory, an entry latency of placing the cache memory into the low power mode based on the number of dirty cache lines, and an exit latency of taking the cache memory out of the low power mode, wherein the low power mode controller is configured to determine the entry latency in part by being configured to determine a time cost of writing the number of dirty cache lines to a second memory based in part on a plurality of measurements of the time cost under different levels of data traffic congestion on an interconnect used to write the dirty cache lines to the second memory,
• determine for the low power mode of the cache memory, an entry power cost of placing the cache memory into the low power mode based on the number of dirty cache lines, and an exit power cost of taking the cache memory out of the low power mode,
• determine if the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost of the cache memory and the entry latency for the cache memory to enter the low power mode;
• and
• place the cache memory in the low power mode in response to a determination that the low power mode for the cache memory results in a power savings over the active mode.

A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) in a portable computing device (PCD), the method comprising:

• identifying a cache memory of the multi-core SoC not being accessed;
• determining for the identified non-accessed cache memory a number of dirty cache lines;
• determining for a low power mode of the cache memory, an entry latency of placing the cache memory into the low power mode based on the number of dirty cache lines, and an exit latency of taking the cache memory out of the low power mode, wherein determining the entry latency includes determining a time cost of writing the number of dirty cache lines to a second memory based in part on a plurality of measurements of the time cost under different levels of data traffic congestion on an interconnect used to write the dirty cache lines to the second memory;
• determining for the low power mode of the cache memory, an entry power cost of placing the cache memory into the low power mode based on the number of dirty cache lines, and an exit power cost of taking the cache memory out of the low power mode;
• determining if the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost of the cache memory and the entry latency for the cache memory to enter the low power mode;
• and
• placing the cache memory in the low power mode in response to a determination that the low power mode for the cache memory results in a power savings over the active mode.

A computer system for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) in a portable computing device (PCD), the system comprising:

• means for identifying a cache memory of the multi-core SoC not being accessed;
• means for determining for the identified non-accessed cache memory a number of dirty cache lines;
• means for determining for a low power mode of the cache memory, an entry latency of placing the cache memory into the low power mode based on the number of dirty cache lines, and an exit latency of taking the cache memory out of the low power mode, wherein the means for determining the entry latency includes means for determining a time cost of writing the number of dirty cache lines to a second memory based in part on a plurality of measurements of the time cost under different levels of data traffic congestion on an interconnect used to write the dirty cache lines to the second memory;
• means for determining for the low power mode of the cache memory, an entry power cost of placing the cache memory into the low power mode based on the number of dirty cache lines, and an exit power cost of taking the cache memory out of the low power mode;
• means for determining if the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost of the cache memory and the entry latency for the cache memory to enter the low power mode;
• and
• means for placing the cache memory in the low power mode in response to a determination that the low power mode for the cache memory results in a power savings over the active mode.