Memory-attached computing resource in network on a chip architecture to perform calculations on data stored on memory external to the chip

A method comprising:

• receiving, by a first set of logical gates configured as a packet reader state machine of a memory-attached computing resource, from a first one of a plurality of computing resources, a packet including (i) a memory address of memory that is external to the computing resource, (ii) one or more operation codes, and (iii) an address of a second one of the plurality of computing resources, wherein the memory-attached computing resource is attached to the memory and the computing resources of the plurality are unattached to the memory, and the memory-attached computing resource and at least a subset of the plurality of computing resources are implemented as a system on a chip;
• accessing, by a second set of logical gates configured as a memory reader state machine of the memory-attached computing resource, the memory and reading data from the memory address;
• processing, by an arithmetic logic unit (ALU) of the memory-attached computing resource, the read data based at least in part on the one or more operation codes;
• accessing, by a third set of logical gates configured as a memory writer state machine of the memory-attached computing resource, the memory and writing the processed data;
• transmitting, by a fourth set of logical gates configured as a packet writer state machine of the memory-attached computing resource, to the address of the second one of the plurality of computing resources, one of the following packets:
• a packet including an indication that the data at the memory address has been processed, or
• a packet including the processed data;
• and
• routing, by a multiplexer included in the memory-attached computing resource, at least the following data:
• the read data from the second set of logical gates configured as the memory reader state machine to the ALU, and
• the processed data from the ALU to the third set of logical gates configured as the memory writer state machine and to the fourth set of logical gates configured as the packet writer state machine.

A computing system comprising:

• a plurality of computing resources communicating with each other using packets,
• wherein a computing resource from among the plurality of computing resources is attached to memory external to the computing system through an external memory interface, and remaining ones of the plurality of computing resources different from the memory-attached computing resource are unattached to the memory,
• wherein at least a portion of the computing system that includes the memory-attached computing resource and at least a subset of the unattached computing resources is implemented as a system on a chip (SoC), and
• wherein the memory-attached computing resource comprises:
• (a) a first set of logical gates configured as a packet reader state machine to decode a packet received from a first one of the plurality of computing resources into state machine parameters including (i) a memory address of the memory, (ii) one or more operation codes, and (iii) an address of a second one of the plurality of computing resources;
• (b) a second set of logical gates configured as a memory reader state machine to read data from the memory address;
• (c) an arithmetic logic unit (ALU) configured to process the read data based at least in part on the one or more operation codes;
• (d) a third set of logical gates configured as a memory writer state machine to write processed data back to the memory;
• (e) a fourth set of logical gates configured as a packet writer state machine to transmit, to the address of the second one of the plurality of computing resources, one of the following packets:
• (i) a packet including an indication that the data at the memory address has been processed, or
• (ii) a packet including the processed data;
• and
• (f) a multiplexer configured to route, within the memory-attached computing resource, at least the following data:
• (i) the read data from the second set of logical gates to the ALU, and
• (ii) the processed data from the ALU to the third set of logical gates and to the fourth set of logical gates.