Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture

A processor apparatus employing an instruction set architecture, the processor apparatus comprising:

• a plurality of processor cores, wherein:
• a first processor core of the plurality of processor cores implements a subset of the instruction set architecture;
• a second processor core of the plurality of processor cores implements an entirety of the instruction set architecture;
• the instruction set architecture specifies a plurality of operand sizes for a first operand type;
• the subset implemented by the first processor core is the instructions that employ a first operand size of the plurality of operand sizes;
• and
• at most one of the plurality of processor cores is active at a given point in time, except during a context switch between two of the plurality of processor cores;
• and
• a processor power manager coupled to the plurality of processor cores, wherein:
• the processor power manager is configured to activate the second processor core and deactivate the first processor core responsive to code that uses one or more operand sizes of the plurality of operand sizes that are different from the first operand size;
• the processor power manager is programmable with a plurality of processor states, wherein each of the plurality of processor states maps to one of the plurality of processor cores;
• the processor power manager is configured to detect that the processor power manager has been programmed to change a current processor state mapped to the second processor core to a requested processor state mapped to the first processor core during a time that code is being executed by the second processor core;
• cause the change to the requested power state and a transfer of a processor context from the second processor core to the first processor core in response to being programmed to change from the current processor state to the requested processor state and further in response detecting that the code uses only the first operand size, wherein the first processor core is configured to continue execution of the code responsive to the transfer;
• and
• the processor power manager is configured to prevent the change to the requested power state and prevent the transfer to the first processor core and continue execution of the code the second processor core responsive to the code using the one or more operand sizes.

A method comprising:

• executing first code on a first processor core of a plurality of processor cores forming a processor, wherein the first code is coded to an instruction set architecture that specifies a plurality of operand sizes for a first operand type, and wherein the first processor core implements only a first operand size of the plurality of operand sizes, wherein a first instruction is executable by the first processor core in the event that the first instruction uses the first operand size and the first instruction is not executable by the first processor core in the event that the first instruction uses a different operand size of the plurality of operand sizes;
• determining that the first code uses one or more operand sizes of the plurality of operand sizes that are different from the first operand size, wherein the one or more operand sizes are implemented on a second processor core of the plurality of cores, and wherein the first instruction is executable by the second processor core with any of the plurality of operand sizes;
• transferring a processor context from the first processor core to the second processor core responsive to the determining;
• executing the first code on the second processor core;
• operating the second processor core responsive to a first operating point;
• detecting a change to a second operating point of the processor during a time that the first code is executing on the second processor core, wherein the second operating point is mapped to the first processor core;
• and
• responsive to determining that the first code uses the one or more operand sizes:
• preventing the change to the second operating point;
• preventing a transfer of the processor context to the first processor core;
• and
• continuing execution of the first code on the second processor at the first operating point.