Method and apparatus for controlling an operating mode of a processing module

Power mode control circuitry to control an operating mode of a processing module, the power mode control circuitry to:

• receive an indication of the execution of at least one background task by the at least one processing module;
• aggregate an execution duration for the at least one background task on the at least one processing module;
• and
• determine whether the aggregated execution duration for the at least one background task exceeds a threshold duration within one of a plurality of repeated evaluation periods;
• and
• if the aggregated execution duration for the at least one background task exceeds a threshold duration within one of the repeated evaluation periods:
• switch a power mode for the at least one processing module to a lower power mode from a higher power mode when the at least one background task is allocated to the at least one processing module for execution thereon;
• while the at least one processing module is in the lower power mode, switch the at least one processing module from the lower power mode to the higher power mode when a timing-critical task is allocated to the at least one processing module for execution thereon;
• receive a reset signal in response to an expiration of the one of the repeated evaluation periods;
• and
• reset the aggregated execution duration for the at least one background task in response to receiving the reset signal.

A method of controlling an operating mode of a processing module, the method comprising:

• receiving an indication of the execution of first and second background tasks by the processing module;
• aggregating an execution duration for the first and second background tasks on the processing module;
• determining whether the aggregated execution duration for the at least one background task exceeds a threshold duration within one of a plurality of repeated evaluation periods;
• and
• if the aggregated execution duration for the first and second background tasks exceeds a threshold duration within one of the repeated evaluation periods:
• switching a power mode for the at least one processing module to a lower power mode from a higher power mode when the first and second background tasks are allocated to the at least one processing module for execution thereon;
• while the at least one processing module is in the lower power mode, switching the at least one processing module from the lower power mode to the higher power mode when a timing-critical task is allocated to the at least one processing module for execution thereon;
• receiving a reset signal in response to an expiration of a timer of a first evaluation period of the one of the repeated evaluation periods;
• and
• resetting the aggregated execution duration for the first and second background tasks in response to receiving the reset signal.