Method and system for providing instant responses to sleep state transitions with non-volatile random access memory

An apparatus comprising:

• a processor in a computer system;
• and
• an interface for the processor to communicate to a non flash non-volatile random access system memory component that is accessible to the processor through a system memory interface and without passing through an I/O subsystem of the computer system, the non flash non-volatile random access system memory component being byte-rewritable by the processor, the non flash non-volatile random access memory component to behave as system memory for the computing system during the computer system's normal operating mode;
• wherein upon a request for the computer system to enter a powered sleep state, the processor is to convert the powered sleep state into a powered-off sleep state with system memory context stored in the non flash non-volatile random access system memory component such that the system memory context is to remain stored in the non flash non-volatile random access system memory component and is not transferred to a non volatile mass storage component as part of the conversion to the powered-off sleep state, the powered sleep state defined as a state in which power is supplied to volatile random access memory in the computer system and the powered-off sleep state defined as a state in which power is removed from the volatile random access memory;
• and
• wherein upon a wake event, the computer system is to execute BIOS initialization program code from the non flash non-volatile random access system memory component without loading the BIOS initialization program code into the non flash non-volatile random access system memory component from the non volatile mass storage component between the wake event and the executing, the execution of the BIOS initialization program code to resume working state operations using the system memory context stored in the non-volatile random access system memory component.

A system comprising:

• a processor in a computer system;
• a dynamic random access memory (DRAM) coupled to the processor;
• and
• a non flash non-volatile random access system memory component coupled to the processor and accessible by the processor through a system memory interface and without passing through an I/O subsystem of the computer system, the non flash non-volatile random access system memory component being byte-rewritable by the processor, the non flash non-volatile random access memory component to behave as system memory for the computing system during the computer system's normal operating mode;
• wherein upon a request for the computer system to enter a powered sleep state, the processor converts the powered sleep state into a powered-off sleep state with system memory context stored in the non flash non-volatile random access system memory component such that the system memory context is to remain stored in the non flash non-volatile random access system memory component and is not transferred to a non volatile mass storage component as part of the conversion to the powered-off sleep state, the powered sleep state defined as a state in which power is supplied to the DRAM and the powered-off sleep state defined as a state in which power is removed from the DRAM, and wherein upon a wake event, the computer system executes BIOS initialization program code from the non flash non-volatile random access system memory component without loading the BIOS initialization program code into the non flash non-volatile random access system memory component from the non volatile mass storage component between the wake event and the execution of the BIOS initialization program code, the execution of the BIOS initialization program code to resume working state operations using the system memory context stored in the non flash non-volatile random access system memory component.