Systems and methods to separate power domains in a processing device

A semiconductor device comprising:

• a processing core having a plurality of sub cores;
• a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core;
• and
• a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device, wherein each of the cells comprises:
• a floating gate structure;
• and
• a plurality of diffusion breaks along an extent of the cell.

A semiconductor chip comprising:

• a plurality of processing cores disposed within semiconductor material of the semiconductor chip, a first one of the processing cores having a first sub core and a second sub core;
• a power rail spanning from the first sub core to the second sub core, the power rail including conductive lines within the semiconductor material;
• and
• a cell abutting the first sub core and the second sub core on the power rail, the cell providing a discontinuity in the power rail at a plurality of metal layers of the conductive lines;
• an additional power rail perpendicular to the power rail and in communication with the power rail within the first sub core;
• and
• an additional cell providing a discontinuity in the additional power rail.

A semiconductor chip having a processing core, the processing core comprising:

• a first sub core;
• a second sub core;
• means for distributing power to the first sub core and the second sub core;
• and
• means for providing discontinuities in the power distributing means at multiple metal layers of the semiconductor chip, wherein a boundary between the first sub core and the second sub core is defined by the discontinuity providing means abutting the first sub core and the second sub core, wherein the processing core comprises a Graphics Processing Unit (GPU), and wherein the first sub core comprises a shader unit, and wherein the second sub core comprises an accumulator unit.