Generalized resettable memory

A non-transitory computer readable medium comprising instructions, the instructions when executed by at least a processor causing the processor to configure a field programmable gate array (FPGA) to implement a resettable memory device, the instructions configuring the FPGA to:

• implement a non-resettable memory unit having a plurality of cells for storing states of signals;
• implement a reset status indicator circuit having a storage component that stores indicators, each indicator indicating whether states of corresponding cells should be reset or not;
• implement a sequential logic sampling circuit configured to receive a variable test input signal and generate logic computation result by performing sequential logic computation according to the variable test input signal;
• and
• implement a multiplexer comprising a first input, a second input, and a control input, the first input coupled to an output of the non-resettable memory unit, the second input coupled to an output of the sequential logic sampling circuit, the control input coupled to an output of the reset status indicator circuit, the multiplexer configured to:
• receive an indicator associated with a subset of cells from the plurality of cells through the control input,
• responsive to the indicator indicating states of the subset of cells should not be reset, output states of the subset of cells, the states of the subset of cells received from the non-resettable memory unit through the first input, and
• responsive to the indicator indicating the states of the subset of cells should be reset, output logic computation result as reset values of the subset of cells, the logic computation result received from the sequential logic sampling circuit through the second input, the reset values of the subset of cells changed during different time periods according to states of the variable test input signal changing during the different time periods.

An emulator comprising:

• a non-resettable memory unit having a plurality of cells for storing states of signals;
• a reset status indicator circuit having a storage component that stores indicators, each indicator indicating whether states of corresponding cells should be reset or not;
• a sequential logic sampling circuit configured to receive a variable test input signal and generate logic computation result by performing sequential logic computation according to the variable test input signal;
• and
• a multiplexer comprising a first input, a second input, and a control input, the first input coupled to an output of the non-resettable memory unit, the second input coupled to an output of the sequential logic sampling circuit, the control input coupled to an output of the reset status indicator circuit, the multiplexer configured to:
• receive an indicator associated with a subset of cells from the plurality of cells through the control input,
• responsive to the indicator indicating states of the subset of cells should not be reset, output states of the subset of cells, the states of the subset of cells received from the non-resettable memory unit through the first input, and
• responsive to the indicator indicating the states of the subset of cells should be reset, output logic computation result as reset values of the subset of cells, the logic computation result received from the sequential logic sampling circuit through the second input, the reset values of the subset of cells changed during different time periods according to states of the variable test input signal changing during the different time periods.