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US 9,958,746 B2Granted
Liquid crystal display
AssigneeLG Display Co., Ltd.
InventorChungSik Kong
Life of this patent
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Abstract
Disclosed herein is a liquid crystal display in which a hole is shared by thin-film transistors to thereby improve the aperture ratio. The liquid crystal display includes a substrate, a first thin-film transistor and a second thin-film transistor on the substrate. In the planarization film, a single hole is disposed to expose a portion of the source electrode or the drain electrode from each of the first thin-film transistor and the second thin-film transistor. Each of the first and second pixel electrodes is connected to the source electrode or the drain electrode of the first and second thin-film transistors via the single hole in the planarization film. Accordingly, the area of a black matrix is reduced and thus the aperture ratio of the liquid crystal display 100 can be improved.
Claims18
A liquid crystal display comprising:
- a substrate;
- a first thin-film transistor and a second thin-film transistor on the substrate, each of the first and second thin-film transistors comprising an active layer, a gate electrode, a source electrode and a drain electrode;
- a planarization film over the first thin-film transistor and the second thin-film transistor having a single hole such that at least a part of a top surface of the source electrode or the drain electrode of each of the first thin-film transistor and the second thin-film transistor is not covered by the planarization film;
- a first pixel electrode being in direct contact with at least the part of the top surface of the source electrode or the drain electrode of the first thin-film transistor and disposed on the planarization film;
- a second pixel electrode being in direct contact with at least the part of the top surface of the source electrode or the drain electrode of the second thin-film transistor and disposed on the planarization film;
- an upper substrate facing the substrate;
- a latch column spacer on the upper substrate, the latch column spacer being located between the first thin-film transistor and the second thin-film transistor within a region of the single hole;
- and
- a cell gap column spacer on the upper substrate,
- wherein the first pixel electrode and the second pixel electrode are connected to the source electrode or the drain electrode of the first thin-film transistor and that of the second thin-film transistor, respectively, via the single hole of the planarization film.
7 more elements
A liquid crystal display comprising:
- a substrate having an array of pixels, each pixel having a plurality of sub-pixel regions;
- a first gate line and a second gate line on the substrate;
- a first thin-film transistor and a second thin-film transistor between the first gate line and the second gate line, each of the first and second thin-film transistors comprising an active layer, a gate electrode, a source electrode and a drain electrode;
- a planarization film over the first thin-film transistor and the second thin-film transistor, the planarization film having a single hole between the first gate line and the second gate line;
- a first pixel electrode in a first sub-pixel region of a first pixel disposed on the planarization film and connected to a top surface of the source electrode or the drain electrode of the first thin-film transistor via the single hole;
- a second pixel electrode in a second sub-pixel region of a second pixel disposed on the planarization film and connected to a top surface of the source electrode or the drain electrode of the second thin-film transistor via the single hole, wherein the first pixel electrode and the second pixel electrode are spaced apart from each other in the single hole;
- an alignment film disposed over the first pixel electrode and the second pixel electrode;
- and
- a column spacer located above the alignment film, and between the first thin-film transistor and the second thin-film transistor within a region of the single hole in the planarization film,
- wherein the column spacer is fitted in the single hole in the planarization film with a margin of at least 5 μm and a size of the single hole is larger than a size of the column spacer.
7 more elements
A display device comprising:
- an array of thin-film transistors (TFTs) on a substrate having a matrix of pixels;
- an array of pixel electrodes over the array of TFTs and corresponding to the matrix of pixels;
- a planarization film over the array of TFTs and configured to have a plurality of common contact holes;
- and
- a latch column spacer provided within one or more of the common contact holes,
- each common contact hole being configured to allow electrical connection of two adjacent TFTs to their respective pixel electrodes by being commonly shared by the two adjacent TFTs, and each common contact hole is located between two adjacent gate lines on the substrate, wherein each of the two adjacent pixel electrodes is connected to each of two adjacent TFTs in the common contact hole and each of the two adjacent pixel electrodes is spaced apart from each other in the common contact hole,
- wherein the latch column spacer is at a position corresponding to a position of each common contact hole and located between the two adjacent TFTs within the position of each common contact hole.
4 more elements
Dependencies are inferred from the claim text.