Tap SPC with tap state machine reset and clock control

An integrated circuit, comprising:

• A. tap domain test access port circuitry having a test data in (TDI) input lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data out (TDO) output lead;
• and
• B. serial to parallel control circuitry having a data I/O (DIO) lead and a clock (CLK) input lead, the serial to parallel control circuitry having a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the CLK input lead, and a TDO input lead coupled to the TDO output lead, the serial to parallel control circuitry including:
• i. serial input parallel output circuitry having a serial input connected to the data I/O DIO lead, a clock input connected with the clock input lead, a TDI output, and a TMS output;
• ii. update register circuitry having a first input connected to the TDI output of the serial input parallel output circuitry and a first output connected to the TDI output lead, having a second input connected to the TMS output of the serial input parallel output circuitry and a second output connected to the TMS output lead, and having an update clock (UCK) input;
• iii. tap state machine circuitry separate from the tap domain test access port circuitry, the tap state machine circuitry having a TCK input connected to the TCK output lead, a TMS input connected to the TMS output lead, and a reset output, the tap state machine circuitry being free of connections to the tap domain test access port circuitry;
• and
• iv. clock controller circuitry having an input connected to the CLK clock input lead, an update clock UCK output connected to the update UCK clock input, a test clock output lead connected to the TCK output lead, and a reset input connected to the reset output.