Structure for interconnect parasitic extraction

A structure for extracting interconnect parasitic in a ring oscillator circuit comprising N logical units connected in head to tail series to form a ring oscillator and at least one frequency divider, an input port of the frequency divider is connected to an output port of one of the logical units, wherein N is an odd number and is greater than or equal to 3;

• the structure comprises parasitic resistance sub-structures and/or parasitic capacitance sub-structures;
• wherein each of the parasitic resistance sub-structures is connected to metal lines in a metal interconnect layer between a corresponding logical unit and its adjacent logical unit for determining errors in extracting parasitic resistance of polysilicon interconnects or metal interconnects;
• wherein each of the parasitic capacitance sub-structures is connected to a corresponding logical unit in parallel with one end connected to an input port of the corresponding logical unit through the metal lines in the metal interconnect layer and the other end to a reference voltage, for determining errors in extracting parasitic capacitance in relation to the polysilicon interconnects or the metal interconnects;
• wherein a parasitic extraction error is determined by comparing RC delay simulation results of the ring oscillator circuit having the structure with its actual RC delay measurement results.