3D semiconductor device and system
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
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Abstract
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.
Claims20
A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor;
- and
- a third transistor,
- wherein said third transistor is overlaying said second transistor and said third transistor is controlled by a third control line,
- wherein said second transistor is overlaying said first transistor and said second transistor is controlled by a second control line,
- wherein said first transistor is part of a control circuit controlling said second control line and said third control line,
- wherein said second transistor and said third transistor are self-aligned.
A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor;
- and
- a third transistor,
- wherein said third transistor is overlaying said second transistor and said third transistor is controlled by a third control line,
- wherein said second transistor is overlaying said first transistor and said second transistor is controlled by a second control line,
- wherein said second transistor comprises a schottky barrier, and
- wherein said second transistor and said third transistor are self-aligned.
A 3D integrated circuit device, comprising:
- a first transistor;
- a first memory cell comprising a second transistor;
- and
- a second memory cell comprising a third transistor,
- wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,
- wherein said first transistor is part of a control circuit controlling said first memory cell and second memory cell,
- wherein said second transistor is self-aligned to said third transistor, and
- wherein said second transistor is connected to said third transistor with an ohmic connection.
Dependencies are inferred from the claim text.