Refresh control circuit for target refresh operation of semiconductor memory device, and operating method thereof
AssigneeSK hynix Inc.
InventorJung-Hyun Kim
Life of this patent
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Abstract
A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to a target address.
Claims20
A semiconductor memory device comprising:
- a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines;
- and
- a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, generating a target address by counting the number of identical external addresses among external addresses that are inputted in response to an active signal, counting the number of the active signals that are inputted between at least two neighboring refresh signals, regardless of the external addresses, and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to the target address.
A refresh control circuit comprising:
- an activator suitable for counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, generating a row hammering activating signals;
- a refresh selector suitable for generating a first refresh selection signal and a second refresh selection signal in response to the refresh signal and the row hammering activating signal;
- a row hammering address detector that is activated in response to the row hammering activating signal, suitable for counting the number of identical external addresses among external addresses that are inputted whenever an active signal is activated, and when the counted number of the identical external addresses is equal to or greater than a predetermined number, detecting a row hammering address;
- a first refresh address generator suitable for generating a first refresh address by counting the refresh signal;
- a second refresh address generator that is activated in response to the row hammering activating signal, suitable for generating a second refresh address calculated based on the row hammering address;
- and
- an address selector suitable for selecting the first refresh address or the second refresh address in response to the first refresh selection signal and the second refresh selection signal.
An operating method of a semiconductor memory device, comprising:
- sequentially performing a first refresh operation onto a plurality of word lines in response to a refresh signal;
- generating a target address by counting the number of identical external addresses among external addresses that are inputted in response to an active signal;
- and
- counting the number of the active signals that are inputted between at least two neighboring refresh signals, regardless of the external addresses, and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to the target address.
Dependencies are inferred from the claim text.