# US 9,953,170 B2 · Semiconductor memory device, semiconductor system and reading method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,953,170 B2 - Document ID: US9953170B2 - Status: Granted - Kind: B2 - Application number: 14/567,326 - Filed: 2014-12-11 - Published: 2015-11-12 - Granted: 2018-04-24 - Earliest claimed: 2014-05-08 - Assignees: Winbound Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Takehiro Kaminaga - Web page: https://patentgrep.com/patent/US9953170B2 ## CPC - G06F 21/60: Protecting data - G06F 3/061: {Improving I/O performance} - G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 9/00: Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10) - G06F 21/575: {Secure boot} - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F 2221/2135: Metering - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The invention provides a flash memory which may effectively protect information with a high security level. A flash memory includes a setting part. When the setting part is inputted a specific command, the setting part sets up specific address information to a nonvolatile configuration register, and sets up specific data in a hidden storage region. The flash memory also includes: a comparing part, which compares inputted address information and the specific address information during a reading operation; and a control part, which reads specific data set in the storage region and erases a specific address when two address information are consistent, and reads data stored in a memory array according to the inputted address information when two address information are inconsistent. ## Claims ### Claim 1 A semiconductor memory device, comprising: a NAND memory array; an input part, inputting an address information, a data, and a specific command which instructs to store a first address information and a first data, wherein the specific command is received from a host device, and comprises the first address information and the first data; a reading part, reading the data stored in the NAND memory array based on the address information input from the input part; a setting part, storing the first address information in an address storage region of the semiconductor memory device as a specific address information according to the inputted specific command, wherein the setting part storing the first data in a hidden data storage region of the semiconductor memory device as a specific data according to the inputted specific command, wherein the first data is not stored in a first address, of the NAND memory array, indicated by the first address information; and a control part, controlling the reading part, wherein the control part, during a reading operation, compares the specific address information with a second address information input from the input part, wherein the reading operation is for reading a second data stored in a second address of the NAND memory array which indicated by the second address information, wherein when the second address information and the specific address information are inconsistent, the reading part does not read the specific data from the hidden data storage region, but reads the second data from the second address of the NAND memory array according to the second address information, wherein when the second address information and the specific address information are consistent, the control part erases or invalidates the specific address information stored in the address storage region, and the reading part reads the specific data from the hidden data storage region. ### Claim 2 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the setting part comprises a non-volatile address storage region and a volatile address storage region, and the address storage region is the non-volatile address storage region, wherein the setting part transmits and stores the specific address information stored in the non-volatile address storage region to the volatile address storage region after a power is turned on, and the control part erases the specific address information stored in the volatile address storage region when the second address information and the specific address information are consistent. ### Claim 3 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the specific address information also serves as an address allowing to select an address space of the NAND memory array. ### Claim 4 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the hidden data storage region is set in a region different from a memory array that a user is able to use. ### Claim 5 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the address storage region is a configuration register. ### Claim 6 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the control part comprises a counting part, the counting part counts the number of times that the second address information input from the input part and the specific address information are consistent, and in the operation of the control part erases or invalidates the specific address information stored in the address storage region when the second address information and the specific address information are consistent, the control part erases or invalidates the specific address information when an outcome of counting of the counting part reaches a predetermined value. ### Claim 7 (depends on 1) A semiconductor system, comprising the semiconductor memory device as claimed in claim 1 and a host device connected to the semiconductor memory device, wherein the host device outputs the specific address information and the specific data to the semiconductor memory device through the specific command. ### Claim 8 A reading method for reading a specific data in a system comprising a semiconductor memory device and a host device, comprising: outputting a specific command to the semiconductor memory device by the host device, wherein the specific command comprises a specific address information and a specific data, and instructs to store the specific address information and the specific data; according to the specific command, storing the specific address information to an address storage region of the semiconductor memory device, and storing the specific data to a hidden data storage region of the semiconductor memory device, wherein the specific data is not stored in a first address, of the NAND memory array, indicated by the specific address information; during a reading operation, comparing the specific address information with an input address information corresponding to the reading operation, wherein the reading operation is for reading a data stored in a second address, which indicated by the input address information, of the NAND memory array of the semiconductor memory device; when the input address information and the specific address information are inconsistent, not reading the specific data from the hidden data storage region, but read the data from the second address of the NAND memory array according to the input address information, when the input address information and the specific address information are consistent, erasing or invalidating the specific address information stored in the address storage region, and reading the specific data from the hidden data storage region. ### Claim 9 (depends on 8) The reading method as claimed in claim 8, wherein the semiconductor memory device comprises a non-volatile address storage region and a volatile address storage region, and the address storage region is the non-volatile address storage region, wherein the reading method further comprises transmitting and storing the specific address information stored in a non-volatile address storage region to the volatile address storage region after a system power is turned on, and erasing the specific address information of the volatile address storage region when the input address information and the specific address information are consistent. ### Claim 10 (depends on 8) The reading method as claimed in claim 8, wherein the reading method further comprises: counting the number of times that the input address information and the specific address information are consistent; and erasing or invalidating the specific address information when an outcome of counting reaches a predetermined value.