High performance read-modify-write system providing line-rate merging of dataframe segments in hardware

A circuit, comprising:

• a merge multiplexer;
• first and second multiplexers, wherein the first multiplexer is configured to output sectors of a second data frame to the second multiplexer and the merge multiplexer;
• third and fourth multiplexers, wherein the third multiplexer is configured to output sectors of a first data frame to the fourth multiplexer and the merge multiplexer;
• and
• a logic device configured to:
• input sectors of the first data frame and the second data frame that are output from the fourth multiplexer and the second multiplexer, respectively;
• and
• perform an error check on a first check-data frame comprising the sectors corresponding to sectors in the first data frame and a second check-data frame comprising the sectors corresponding to sectors in the second data frame;
• wherein the merge multiplexer is configured to merge one or more sectors from the first multiplexer with one or more sectors from the second multiplexer based on a merge mask to form a merged output data frame,
• wherein at least some of the sectors in the first and second check-data frames are transmitted on a subset of a plurality of data paths different from a subset of the plurality of data paths that transmits sectors of the merged output data frame, and
• wherein the error check verifies the merged output data frame.