Digital controller architecture for three-phase AC sources

A digital controller for three phase AC sources, comprising:

• a first, a second, and a third controller;
• the first controller having a phase accumulator and command control, the output of the phase accumulator and command control providing input to a waveform synthesizer and a command processor, and the waveform synthesizer providing a reference input to a control loops and the command processor providing a command input to the control loops and a synchronization generator providing an input to the control loops, and the control loops providing an input to a pulse width modulator and the pulse width modulator providing an input to the power stage and the power stage providing a feedback to the control loops;
• the second controller receiving and adding the output of the phase accumulator and the command control to provide an input to a second controller waveform synthesizer, and the outputs of the phase accumulator and command control forming an input to a second controller command processor, and the second controller waveform synthesizer providing an input to a second controller control loops and the second controller command processor providing an input to the second controller control loops and the synchronization generator providing an input to the second controller control loops, and the second controller control loops providing an input to a second controller pulse width modulator and the second controller pulse width modulator providing an input to the second power stage and the second power stage providing a feedback to the second controller control loops;
• and
• the third controller receiving and adding the output of the phase accumulator and the command control to provide an input to a third controller waveform synthesizer, and the outputs of the phase accumulator and command control forming an input to a third controller command processor, and the third controller waveform synthesizer providing an input to a third controller control loops and the third controller command processor providing an input to the third controller control loops and the synchronization generator providing an input to the third controller control loops, and the third controller control loops providing an input to a third controller pulse width modulator and the third controller pulse width modulator providing an input to the third power stage and the third power stage providing a feedback to the third controller control loops.