US 9,947,467 B2Granted

Protected capacitor system and method

OwnerMark Eugene Goodsoninventor

Life of this patent

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Abstract

A protected capacitor system/method implementing enhanced transient over-voltage suppression is disclosed. The system/method incorporates one or more surge suppression devices (SSDs) proximally located and in parallel with a capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions. The SSDs are formed from series combinations of transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across a capacitor structure to locally suppress voltage transients across the capacitor structure in excess of the voltage rating of the capacitor structure. The parallel shunting TVS/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated in an enclosure incorporating the capacitor structure.

Claims20

Dependent claims

A protected capacitor system comprising:

(a) capacitor enclosure (CPE);
(b) capacitor cover (CPC);
(c) non-polarized capacitor (NPC);
(d) printed circuit board (PCB);
(e) transient voltage surge suppressor (TVS);
and
(f) semiconductor P-N diode (PND);
wherein:
said CPE is configured as a shell having an open cavity end (OCE) and an open cavity void (OCV) configured to contain said NPC and said PCB;
said CPC is configured to cover and seal said OCE;
said NPC and said PCB are contained within said OCV;
said CPC comprises a first terminal connection (FTC) and a second terminal connection (STC);
said FTC and said STC are insulated from said CPC and extend through an outer surface of said CPC;
said NPC comprises a first capacitor connection (FCC) and a second capacitor connection (SCC);
said TVS comprises a first TVS connection (FVC) and a second TVS connection (SVC);
said PND comprises a first PND connection (FPC) and a second PND connection (SPC);
said SVC is electrically coupled to said FPC via metal traces on said PCB;
said TVS and said PND form a surge suppression device (SSD) having a first SSD terminal (FDC) electrically coupled to said FVC and a second SSD terminal (SDC) electrically coupled to said SPC;
said PCB comprises a first input connection (FIC), a second input connection (SIC), a first output connection (FOC), and a second output connection (SOC);
said PCB comprises metal traces configured to electrically couple said FTC, said FIC, said FOC, and said FDC;
said PCB comprises metal traces configured to electrically couple said STC, said SIC, said SOC, and said SDC;
said FCC is electrically coupled to said FOC;
and
said SCC is electrically coupled to said SOC.

21 more elements

A protected capacitor method wherein said method utilizes protected capacitor system comprising:

(a) capacitor enclosure (CPE);
(b) capacitor cover (CPC);
(c) non-polarized capacitor (NPC);
(d) printed circuit board (PCB);
(e) transient voltage surge suppressor (TVS);
and
(f) semiconductor P-N diode (PND);
wherein:
said CPE is configured as a shell having an open cavity end (OCE) and an open cavity void (DCV) configured to contain said NPC and said PCB;
said CPC is configured to cover and seal said OCE;
said NPC and said PCB are contained within said OCV;
said CPC comprises a first terminal connection (FTC) and a second terminal connection (STC);
said FTC and said STC are insulated from said CPC and extend through an outer surface of said CPC;
said NPC comprises a first capacitor convection (FCC) and a second capacitor connection (SCC);
said TVS comprises a first TVS connection (FVC) and a second TVS connection (SVC);
said PND comprises a first PND connection (FPC) and a second PND connection (SPC);
said SVC is electrically coupled to said FPC via metal traces on said PCB;
said TVS and said PND form a surge suppression device (SSD) having a first SSD terminal (FDC) electrically coupled to said FVC and a second SSD terminal (SDC) electrically coupled to said SPC;
said PCB comprises a first input connection (FIC), a second input connection (SIC), a first output connection (FOC), and a second output connection (SOC);
said PCB comprises metal traces configured to electrically couple said FTC, said FIC, said FOC, and said FDC;
said PCB comprises metal traces configured to electrically couple said STC, said SIC, said SOC, and said SDC;
said FCC is electrically coupled to said FOC;
and
said SCC is electrically coupled to said SOC;
with said method comprising the steps of:
(1) placing said NPC, said PCB, and said SSD within said CPE;
(2) covering said OCE of said CPE with said CPC and sealing said CPC to said CPE;
(3) configuring said CPC to electrically couple said FTC to a source of electrical power;
and
(4) configuring said CPC to electrically couple said STC to an electrical load device.

27 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/495,811Filed 24 Apr 2017 · continuation in part
Priority: 25 Apr 2012
Published: US 2017/0229241 A110 Aug 2017
Granted: 17 Apr 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H01G 2/14
Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00: protection against electric or thermal overload
H01G 2/06
Mountings: specially adapted for mounting on a printed-circuit support
H01G 2/10
Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00: housing; Encapsulation
H02H 9/005
Emergency protective circuit arrangements for limiting excess current or voltage without disconnection: avoiding undesired transient conditions

Family

Application13/455,686Parent of this continuation-in-part · filed 25 Apr 2012
Application14/619,619Parent of this continuation · filed 11 Feb 2015
Application14/619,755Parent of this continuation-in-part · filed 11 Feb 2015
Application14/789,270Parent of this continuation-in-part · filed 1 Jul 2015
US 9,093,831 B2Parent of this continuation · filed 28 Jul 2015
US 9,093,832 B2Parent of this continuation-in-part · filed 28 Jul 2015
US 9,634,474 B2Parent of this continuation-in-part · filed 25 Apr 2017
US 2017/0229241 A1Pre-grant publication · published 10 Aug 2017
Application14/789,270Parent of this continuation
Application14/619,619Parent of this continuation-in-part
US 2013/0284490 A1Published application
US 2015/0155694 A1Published application
US 2015/0155695 A1Published application
US 2015/0303673 A1Published application
US 9,947,467 B2This patent

From the US filing history. Foreign family members aren’t listed.