Time delay in digitally oversampled sensor systems, apparatuses, and methods

A system to time delay a signal output from an analog-to-digital converter (ADC), comprising:

• a sensor element, the sensor element is responsive to an analog field quantity:
• a sigma-delta modulator, the sensor element is electrically coupled to the sigma-delta modulator and is configured to produce a pulse density modulated (PDM) output signal at a sampling clock frequency responsive to the analog field quantity;
• and
• a time delay element, the time delay element is electrically configured to receive the PDM output signal, and to output a delayed PDM output signal, wherein the delayed PDM output signal is delayed by a time delay equal to a number of cycles of the sampling clock frequency.

A decimation module for use in an analog-to-digital converter (ADC) system, comprising:

• a general number of N stages, the decimation module having as an input an oversampled digital output signal from a digital sensor;
• an ith stage, the ith stage to low pass filter and to decimate to an ith intermediate sampling rate an ith stage input signal to form an ith stage output signal, wherein the ith intermediate sample rating is less than a sampling clock frequency used to create the oversampled digital output signal;
• a time delay element, the time delay element to delay the ith stage output signal by a delay, wherein the delay is an integer number of ith intermediate sampling rate cycles the time delay element to output a delayed ith stage output signal;
• and
• an i+1 stage, the i+1 stage to receive as an i+1 stage input signal the delayed ith stage output signal, the i+1 stage to low pass filter and to decimate to an i+1 intermediate sampling rate the i+1 stage input signal to form an i+1 stage output signal, wherein the i+1 intermediate sampling rate is lower than the intermediate sampling rate.

A method to delay a signal output from an analog-to-digital converter (ADC), comprising:

• sensing an analog field;
• outputting an oversampled digital signal responsive to the sensing, wherein the oversampled digital signal is created at a sampling clock rate;
• and
• delaying the oversampled digital signal by a time delay wherein the time delay is equal to an integer number of sampling clock cycles to produce a delayed oversampled digital signal.

A non-transitory computer-readable storage medium storing program code for causing a data processing system to perform the steps comprising:

• receiving signals from a digital sensor, the signals are responsive to an analog field;
• processing the signals to create an oversampled digital signal responsive to the receiving, wherein the oversampled digital signal is created at a sampling clock rate;
• and
• delaying the oversampled digital signal by a time delay wherein the time delay is equal to an integer number of sampling clock cycles to produce a delayed oversampled digital signal.

A system to delay a signal output from an analog-to-digital converter (ADC), comprising:

• sensing means for measuring an analog field quantity;
• oversampling means, the oversampling means to oversample a signal detected by the sensing means resulting in an oversampled digital signal;
• delaying means, the delaying means to apply a time delay to the oversampled digital signal, resulting in a delayed oversampled digital signal;
• and decimating means, the decimating means to receive the delayed oversampled digital signal and to low pass filter and to decimate to a lower sampling rate, wherein the resulting digital signal contains a digital representation of the analog field quantity without noise introduced by the oversampling means.

A system to time delay a signal output from an analog-to-digital converter (ADC), comprising:

• a digital sensor responsive to an analog field quantity, the digital sensor configured to output an oversampled digital output signal at a sampling clock frequency;
• a replicator, the replicator to receive the oversampled digital output signal and to output a first replica of the oversampled digital output signal and a second replica of the oversampled digital output signal;
• a first time delay element, the first time delay element is configured to receive as an input the first replica and to output a first time delayed oversampled digital output signal;
• and
• a second time delay element, the second time delay element is configured to receive as an input the second replica and to output a second time delayed oversampled digital output signal.