US 9,941,852 B1 · Operation amplifiers with offset cancellation

Abstract

A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

Claims19

Dependent claims

A semiconductor device comprising:

an operational amplifier including:
a matched pair of transistors including a first transistor and a second transistor;
configuration units, each of the configuration units including a first set of switches, a second set of switches, and an input transistor;
gain adjustment circuitry coupled to adjust gain of the operational amplifier;
measurement circuitry coupled to measure offset in the operational amplifier;
control logic configured to:
operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors;
wherein settings of the first and second sets of switches are selected to minimize the offset.

5 more elements

An operational dance amplifier comprising:

configuration circuits, each of the configuration circuits including an input transistor;
a first transistor including a gate electrode, a first current electrode coupled to a supply voltage, a second current electrode coupled to a current source via a first subset of the configuration circuits and to the gate electrode;
a second transistor including a first current electrode coupled to the supply voltage, a second current electrode coupled to the current source via a second subset of the configuration circuits, and a gate electrode coupled to the gate electrode of the first transistor;
a gain adjustment circuit coupled to adjust an output of the operational amplifier during a calibration mode;
and
control logic configured to calibrate the operational amplifier by testing various subsets of the configuration circuits to determine which of the configuration circuits to include in each of the first and second subsets to minimize offset in the operational amplifier, wherein the input transistors of a first of the various subsets are coupled to the first transistor during the testing and the input transistors of a second of the various subsets are coupled to the second transistor during the testing.

3 more elements

Dependencies are inferred from the claim text.

Operation amplifiers with offset cancellation

Life of this patent

Operation amplifiers with offset cancellation

Life of this patent

Abstract

Claims19