System and method for PAM-4 transmitter bit equalization for improved channel performance

A method, comprising:

• encoding, by a transmitter of a serial data channel, a serial data stream using a quaternary pulse amplitude modulation (PAM-4) scheme into a stream of 2-bit symbols, wherein a particular symbol is represented as a signal at one of four signal levels, and wherein the four signal levels include two balanced pairs of differential signal levels;
• determining, by a hardware de-emphasis circuit of the serial data channel, that a first symbol of the encoded serial data stream is represented as a first instance of a first state of the PAM-4 scheme;
• determining, by the hardware de-emphasis circuit, that a second symbol of the encoded data stream is represented as a second instance of the first state;
• determining, by the hardware de-emphasis circuit, that a third symbol of the encoded serial data stream is represented as a second state of the PAM-4 scheme;
• determining, by the hardware de-emphasis circuit, that the second state is of a same balanced pair as the first state;
• providing, by the hardware de-emphasis circuit, a de-emphasis to a voltage level of the second symbol in response to determining that the second state is of the same balanced pair as the first state;
• determining, by the hardware de-emphasis circuit, that the second state is of a different balanced pair from the first state;
• and
• providing, by the hardware de-emphasis circuit, the de-emphasis and a correction factor to the voltage level of the second symbol in response to determining that the second state is of the different balanced pair from the first state.

A serial data system, comprising:

• a transmitter to encode a serial data stream using a quaternary pulse amplitude modulation (PAM-4) scheme into a stream of 2-bit symbols, wherein a particular symbol is represented as a signal at one of four signal levels, and wherein the four signal levels include two balanced pairs of differential signal levels;
• and
• a hardware de-emphasis circuit to:
• determine that a first symbol of the encoded serial data stream is represented as a first instance of a first state of the PAM-4 scheme;
• determine that a second symbol of the encoded data stream is represented as a second instance of the first state;
• determine that a third symbol of the encoded serial data stream is represented as a second state of the PAM-4 scheme;
• determine that the second state is of a same balanced pair as the first state;
• provide a de-emphasis to a voltage level of the second symbol in response to determining that the second state is of the same balanced pair as the first state;
• determine that the second state is of a different balanced pair from the first state;
• and
• provide the de-emphasis and a correction factor to the voltage level of the second symbol in response to determining that the second state is of the different balanced pair from the first state;
• wherein the hardware de-emphasis circuit comprises a two-tap feed forward equalization (FFE) circuit, and wherein the de-emphasis is provided in one of twenty de-emphasis levels, each de-emphasis level prescribing a different amount of de-emphasis.