RLS-DCD adaptation hardware accelerator for interference cancellation in full-duplex wireless systems

An adaptation hardware accelerator, comprising:

• a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration, wherein the correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the sub-matrices in an upper triangular portion and a diagonal portion of the correlation matrix;
• a DCD core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, in the given calculation iteration based on the correlation data and the cross correlation data, wherein determining the plurality of adaptive weights comprises defining a residual vector comprising the correlation data and determining the plurality of adaptive weights based on the defined residual vector;
• a convergence detector unit configured to determine a convergence parameter;
• a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter, wherein the iteration signal communicates to the calculation unit and the DCD core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the DCD core unit;
• and
• a processor configured to implement instructions associated with one or more of the calculation unit, the DCD core unit, the convergence detector unit, or the controller;
• and
• wherein the defined residual vector is updated in the next calculation iteration together with determining the cross correlation data in the calculation unit, only when the iteration signal indicates the next calculation iteration.

A method for a hardware accelerator, comprising:

• receiving a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determining a correlation data and a cross-correlation data based thereon in a given calculation iteration at a calculation unit;
• determining a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on the correlation data and the cross correlation data at a DCD core unit, by defining a residual vector comprising the cross-correlation data;
• determining a convergence parameter at a convergence detector unit;
• generating an iteration signal based on the convergence parameter at a controller, wherein the iteration signal communicates to the calculation unit and the DCD core unit to continue with a next calculation iteration or to conclude;
• and
• updating the residual vector in the next iteration together with determining the cross correlation data in the calculation unit only when the iteration signal indicates the next iteration,
• wherein one or more of the receiving the plurality of inputs, the determining the plurality of adaptive weights, the determining the convergence parameter, the generating the iteration signal, or the updating the residual vector are implemented via a processor.