Self-biased gyrator-based receiver for amplification and equalization of single-ended signals
AssigneeNVIDIA Corporation
InventorsWalker Joseph Turner, John W. Poulton, Wenxu Zhao
Life of this patent
Estimating the term…
Abstract
A self-biased gyrator-based input receiver amplifies and equalizes single-ended signals. The input receiver implements inductive impedance useful for high-frequency peaking circuits using an active gyrator-C circuit comprising only resistive, capacitive, and transistor elements, which are easily and efficiently fabricated on a conventional integrated circuit. Transistors comprising the input receiver, along with resistive elements and capacitive elements may be implemented as digitally adjustable circuit elements, providing for adjustment of at least peak frequency, low-frequency gain, and termination impedance.
Claims23
A circuit, comprising:
- a first p-channel field-effect transistor (PFET) comprising a first source port, a first drain port, and a first gate port, wherein the first source port is coupled to a positive supply node, the first drain port is coupled to an intermediate output node, and the first gate port is coupled to a feedback node;
- a first n-channel field-effect transistor (NFET) comprising a second source port, a second drain port, and a second gate port, wherein the second source port is coupled to an input node, the second drain port is coupled to the intermediate output node, and the second gate port is coupled to the feedback node;
- a feedback resistive element coupled between the feedback node and the intermediate output node;
- a feedback capacitive element coupled between the feedback node and an alternating current (AC) ground node;
- and
- a termination resistive element coupled between the input node and the negative supply rail.
A circuit, comprising:
- a first p-channel field-effect transistor (PFET) comprising a first source port, a first drain port, and a first gate port, wherein the first source port is coupled to an input node, the first drain port is coupled to an intermediate output node, and the first gate port is coupled to a feedback node;
- a first n-channel field-effect transistor (NFET) comprising a second source port, a second drain port, and a second gate port, wherein the second source port is coupled to a negative supply node, the second drain port is coupled to the intermediate output node, and the second gate port is coupled to the feedback node;
- a feedback resistive element coupled between the feedback node and the intermediate output node;
- a feedback capacitive element coupled between the feedback node and a an alternating current (AC) ground node;
- and
- a termination resistive element coupled between the input node and a positive supply rail.
Dependencies are inferred from the claim text.