Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
AssigneeSanDisk Technologies LLC
InventorsSagar Magia, Jagdish Sabde, Jayavel Pachamuthu
Life of this patent
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Abstract
Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.
Claims26
A method of determining defects in a non-volatile flash memory circuit, comprising:
- programming memory cells of a first plurality of blocks of an array of the non-volatile flash memory circuit;
- subsequently performing an erase operation on the first plurality of blocks, wherein the erase operation includes an alternating series of erase pulses and erase verify operations;
- maintaining, for each the first plurality of blocks, a count of the number erase pulses required for the corresponding block to verify as erased in the erase operation;
- determining from the counts of a second plurality of blocks from the first plurality of blocks an average erase count;
- performing a first defect determination operation on a first block of the first plurality of blocks, including:
- comparing the count for first block to the average erase count;
- and
- in response to the count for the first block exceeding the average erase count by a first number of counts, marking the first block as defective;
- and
- subsequent to the first defect determination operation, performing a stress operation on a group of one or more blocks of the first plurality of blocks, comprising:
- with the group of blocks unselected, applying an erase stress voltage to the group of blocks;
- and
- subsequently programming the group of blocks;
- and
- subsequent to the stress operation, performing a second defect determination operation, comprising:
- performing an erase operation on a first block of the group;
- subsequently reading a second, distinct block of the group;
- determining whether the quality of the data as read from the second block is degraded;
- and
- in response to determining that the data as read from the second block is degraded, marking the second block as defective.
A method of determining defects in a non-volatile flash memory circuit, comprising:
- performing a stress operation on a group of one or more blocks of an array of the non-volatile flash memory circuit, comprising:
- with the group of blocks unselected, applying an erase stress voltage to the group of blocks;
- and
- subsequently programming the group of blocks;
- and
- subsequent to the stress operation, performing a first defect determination operation, comprising:
- performing an erase operation on a first block of the group;
- subsequently reading a second, distinct block of the group;
- determining whether the quality of the data as read from the second block is degraded;
- and
- in response to determining that the data as read from the second block is degraded, marking the second block as defective;
- and
- subsequent to the first defect determination operation, performing a second defect determination comprising:
- subsequently performing an erase operation on the second block of the group;
- subsequently reading a third, distinct block of the group;
- determining whether the quality of the data as read from the third block is degraded;
- and
- in response to determining that the data as read from the third block is degraded, marking the third block as defective.
Dependencies are inferred from the claim text.