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US 9,934,838 B1Granted
Pulse shaping unit cell and array for symmetric updating
AssigneeInternational Business Machines Corporation
InventorsJin-Ping Han, Xiao Sun, Teng Yang
Life of this patent
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Abstract
A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.
Claims25
A memory unit cell, comprising:
- a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback;
- and
- a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.
A memory array device, comprising:
- a plurality of memory unit cells, each comprising:
- a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback;
- and
- a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.
1 more element
Dependencies are inferred from the claim text.