US 9,929,733 B1Granted

Connection propagation for inter-logical block connections in integrated circuits

AssigneeQUALCOMM Incorporated

InventorsPratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du

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Abstract

A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

Claims16

Dependent claims

A 3D integrated circuit device, comprising:

a first tier having at least one first logical block comprising a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin, the first primary output pin lying within a perimeter defined by a total area occupied by logic gates of the at least one first logical block of the first tier;
a timing related or non-functional logic gate of the at least one first logical block between the first primary output pin and a primary output of the first tier, the timing related or non-functional logic gate of the at least one first logic block including a buffer;
a second tier having at least one second logical block comprising a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin, the second primary input pin coupled to the first primary output pin;
and
a timing related or non-functional logic gate of the at least one second logical block between the second primary input pin and a primary input of the second tier, the primary output of the first tier capable of being coupled to the primary input of the second tier.

2 more elements

A 3D integrated circuit device, comprising:

a first tier having at least one first logical block comprising a first primary input pin and a first primary output pin;
means for implementing a first logical function of the at least one first logic block, the first logical function implementing means directly coupled to the first primary output pin;
means for implementing a second logical function of the at least one first logic block, the second logical function implementing means directly coupled to the first primary input pin, the first primary output pin lying within a perimeter defined by a total area occupied by the first and second logical function implementing means of the at least one first logical block of the first tier;
a timing related or non-functional logic gate of the at least one first logical block between the first primary output pin and a primary output of the first tier, the timing related or non-functional logic gate of the at least one first logical block including a buffer;
a second tier having at least one second logical block comprising a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin, the second primary input pin coupled to the first primary output pin;
and
a timing related or non-functional logic gate of the at least one second logical block between the second primary input pin and a primary input of the second tier, the primary output of the first tier capable of being coupled to the primary input of the second tier.

4 more elements

Dependencies are inferred from the claim text.