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US 9,929,011 B2Granted
Formation of heteroepitaxial layers with rapid thermal processing to remove lattice dislocations
AssigneeUltratech, Inc.
InventorsAndrew M. Hawryluk, Ganesh Sundaram, Ritwik Bhatia
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Abstract
Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550° C. and preferable below 350° C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500° C. for less than 12 msec.
Claims10
A process comprising:
- depositing a first layer of first active material onto a coating surface of a substantially single crystal substrate by a physical deposition process;
- wherein the first active material and the substrate have different crystal lattice constraints resulting in a first crystal lattice constraint mismatch;
- wherein the physical deposition process is carried out at a first deposition temperature that is below an expected epitaxial growth temperature associated with the active material;
- and
- heating the first active material layer to a peak annealing temperature that exceeds the expected epitaxial growth temperature by rapid thermal annealing wherein the coating surface is heated to the peak annealing temperature in less than 50 msec;
- wherein the physical deposition process is one of thermal Atomic Layer Deposition and Plasma Enhanced Atomic Layer Deposition wherein the first layer of the first active material comprises a plurality of mono layers of the first active material wherein each mono layer deposited by a single Atomic Layer Deposition coating cycle and the heating step is preformed after the completion of a selected number of Atomic Layer Deposition coating cycles and is repeated after the completion of each multiple of the selected number of Atomic Layer Deposition coating cycles.
3 more elements
A process comprising:
- depositing a first layer of first buffer material onto a coating surface of a substantially single crystal silicon substrate using one of a physical and a chemical deposition process;
- depositing a second layer of a second active material onto a coating surface over the first buffer layer using one of a physical and a chemical deposition process;
- wherein the first buffer material and the second active material have different crystal lattice constraints resulting in a first crystal lattice constraint mismatch there between;
- wherein the first buffer material and the substrate have different crystal lattice constraints resulting in a second crystal lattice constraint mismatch there between;
- wherein the second active material and the substrate have different crystal lattice constraints resulting in a third crystal lattice constraint mismatch there between;
- wherein the each of the first and second crystal lattice constraint mismatches is smaller than the third crystal lattice constraint mismatch;
- depositing the first buffer material at a deposition temperature that is below an expected epitaxial growth temperature associated with the first buffer material;
- heating the first buffer material to a first peak annealing temperature that exceeds the expected epitaxial growth temperature of the first buffer material;
- depositing the second active material at a deposition temperature that is below an expected epitaxial growth temperature associated with the second active material;
- heating the second active material to a second peak annealing temperature that exceeds the expected epitaxial growth temperature of the second buffer material
- wherein each of the heating steps comprises rapid thermal annealing wherein a coating surface of the substrate is heated to the first and the second peak annealing temperature in less than 50 msec and the peak annealing temperature exceeds 550° C.
8 more elements
Dependencies are inferred from the claim text.