System and method for providing an output signal without or with reduced jitter based upon an input signal notwithstanding phase changes in a clock signal

A digital-to-analog converter (DAC) configured to provide an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished notwithstanding one or more phase changes of the clock signal, the DAC comprising:

• a transistor device having first, second, and third terminals, the first terminal being an output terminal in relation to which is communicated the output signal;
• an operational amplifier having an inverting port, a non-inverting port, and an output port, wherein the output port is directly coupled to the second terminal of the transistor device, and either the inverting port or the non-inverting port is directly coupled to the third terminal;
• a first biasing component at least indirectly coupled to either the inverting port or the non-inverting port, and including any of a current source, a voltage source, or a resistor;
• a first component having at least one first switch and a first variable characteristic coupled directly with a first one of the inverting and non-inverting ports;
• a plurality of second components each having a respective additional switch and a respective fixed characteristic, wherein each of the second components is coupled directly with either the first component or a respective other one of the second components,
• wherein respective actuations of the at least one first switch and the additional switches occur at or substantially proximate to respective successive times at which respective level changes in the clock signal occur, respectively, such that the output signal takes on respective increased levels at or substantially proximate to the respective successive times,
• wherein the actuation of the at least one first switch is configured so that, or another action is taken in relation to the first component so that, a first value of the first variable characteristic is at least indirectly applied to or experienced by the first one of the inverting and non-inverting ports at or proximate to a first one of the successive times, and
• wherein due to the first value of the first variable characteristic and each respective fixed characteristic, an effective slope associated with the output signal passes through a starting level at or substantially proximate to a zero-crossing time of the input signal.

A method of providing an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished notwithstanding one or more phase changes of the clock signal relative to the input signal, the method comprising:

• detecting both a first value of the input signal at a first time at which the clock signal experiences a first level change and also a second value of the input signal at a second time at which the clock signal experiences a second level change, the first time preceding a zero-crossing time of the input signal and the second time occurring after the zero-crossing time;
• determining a first change value at least indirectly based upon the first and second values and based upon a standard step height value;
• switching at least one switch so as to cause the output signal to change from a starting level to a first step level based at least in part upon the first change value at or substantially proximate to the second time;
• switching first and second additional switches respectively at or proximate to third and fourth times, respectively, at which the clock signal experiences third and fourth level changes, respectively, so as to cause the output signal to change from the first step level to a second step level and then to a third step level, respectively, at or proximate to the third and fourth times, respectively,
• wherein the starting level, first step level, second step level, and third step level of the output signal are such that an effective slope associated with the output signal passes through the starting level at or substantially proximate to the zero-crossing time,
• whereby, notwithstanding the one or more phase changes in the clock signal, the output signal substantially or entirely retains a consistent phase relative to the input signal over a time period corresponding to a plurality of periods of the clock signal.