Integrated circuit wafer integration with catalytic laminate or adhesive
AssigneeSierra Circuits, Inc.
InventorsKenneth S. Bahl, Konstantine Karavakis
Life of this patent
Estimating the term…
Abstract
A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
Claims20
An integrated circuit package comprising:
- a catalytic laminate having a first surface and a second surface opposite the first surface, the catalytic laminate having catalytic particles dispersed an exclusion depth below said first surface and said second surface, the catalytic laminate thereby having a lower density of catalytic particles in a region from said first surface to said exclusion depth or from said second surface to said exclusion depth than other regions of said catalytic laminate;
- a plurality of apertures in said catalytic laminate, at least one said aperture located adjacent to a land of an integrated circuit for attachment;
- a plurality of channels formed onto said second surface of said catalytic laminate, at least one said channel extending from an aperture to a terminal land on said second surface;
- said plurality of channels, said plurality of apertures, and at least one said integrated circuit land having exposed catalytic particles such that a conductor is formed by electroless deposition of copper which interconnects at least one said integrated circuit land, at least one said channel, and said terminal land on said second surface.
A process for forming an integrated circuit package, the process operative on an integrated circuit having electrically conductive lands and a catalytic laminate having a first surface and a second surface opposite the first surface, each said first surface and said second surface having a reduced density of catalytic particles in a region extending from said first surface to an exclusion depth below said first surface and also from said second surface to an exclusion depth below said second surface compared to other regions of the catalytic laminate, the process comprising:
- forming apertures into the catalytic laminate in locations corresponding to integrated circuit lands, said apertures thereby exposing said catalytic particles of said catalytic laminate;
- forming channels to a depth below the exclusion depth leading to said apertures and also to optional connection regions on said second surface;
- performing an electroless plating operation until said channels and apertures are in electrical contact with said integrated circuit lands and said optional connection regions.
An integrated circuit package comprising:
- an integrated circuit chip having electrically conductive lands;
- a catalytic resin applied to the integrated circuit, said catalytic resin comprising a resin mixed with catalytic particles;
- said catalytic resin cured to said integrated circuit chip, said curing performed such that an exposed surface of said catalytic resin does not have exposed catalytic particles in a region extending from said catalytic resin exposed surface to an exclusion depth below said catalytic resin surface;
- said catalytic resin having a plurality of apertures, at least one said aperture positioned adjacent to one of said integrated circuit chip lands;
- a plurality of device electrical attachments formed in channels in said exposed surface of said catalytic resin, said channels having a depth greater than said exclusion depth, said channels disposed to provide interconnecting paths from said integrated circuit chip lands to package terminals;
- where said channels and said apertures have surfaces coated with copper.
A process for forming an integrated circuit package, the process operative on an integrated circuit with conductive lands, the process comprising:
- applying a catalytic laminate to a surface of the integrated circuit, said catalytic laminate having catalytic particles below an exclusion depth;
- forming apertures in said catalytic laminate adjacent to said conductive lands;
- forming device leads in the catalytic laminate;
- forming channels having a depth greater than the exclusion depth in the laminate which interconnect at least one said integrated circuit land to at least one device terminal;
- electroless plating said integrated circuit package, thereby connecting said device terminals and said at least one integrated circuit conductive land.
Dependencies are inferred from the claim text.