Direct memory access controller
AssigneeMicrochip Technology Incorporated
InventorsJoseph W. Triece, Rodney J. Pesavento, Gregg D. Lahti, Steven Dawson
Life of this patent
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Abstract
A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.
Claims20
A microcontroller comprising:
- a bus;
- a central processing unit (CPU) coupled with said bus;
- a memory coupled with said bus;
- a plurality of peripherals coupled with the bus;
- a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from said CPU and being coupled with said bus, wherein for access to said bus said DMA controller is programmable in a first mode to have priority over said CPU and the plurality of peripherals and in a second mode to immediately suspend data transfer on all DMA channels and grant the CPU direct access to the bus.
A method for performing a data transmission over a bus coupled with a master device and a direct memory access (DMA) controller having a plurality of DMA channels;
- the method comprising:
- providing the master device coupled with the bus, a memory coupled with the bus, a plurality of peripheral devices coupled with the bus and the DMA controller coupled with the bus within a microcontroller;
- assigning each of said plurality of DMA channels a priority level;
- upon request for a DMA data transmission, granting the DMA controller access to said bus with one of said plurality of DMA channels;
- feeding a suspend command having a priority level to said DMA controller;
- if said priority level in said suspend command is higher than a priority level of said DMA channel having access to said bus, then
- suspending any DMA channel having a lower priority than said priority level in said suspend command from accessing said bus;
- if no other DMA channel has access to said bus, then
- granting the master device access to said bus;
- performing at least one bus access by said master device;
- feeding a resume command to said DMA controller to resume said DMA data transmission.
Dependencies are inferred from the claim text.