Hybrid MOS-PCM CMOS SOI switch

An integrated circuit (IC) switch configured to control signals transmitted along a signal path, the switch comprising:

• a plurality of Metal-Oxide-Silicon (MOS) transistors coupled in series in the signal path;
• and
• a plurality of switching elements connected in parallel and disposed in the signal path, wherein each said switching element comprises a Phase Change Material (PCM) structure,
• wherein each of the plurality of MOS transistors is configured to apply a first OFF-capacitance to the signal path when said each MOS transistor is in a high-resistance state,
• wherein the plurality of switching elements are configured to collectively apply a second OFF-capacitance to the signal path when all of said plurality of switching elements are in a high-resistance state such that said second OFF-capacitance is substantially equal to or lower than said first OFF-state capacitance of said each MOS transistor.

An integrated circuit (IC) switch configured to control signals transmitted along a signal path, the switch comprising:

• a plurality of Metal-Oxide-Silicon (MOS) transistors coupled in series in the signal path;
• and
• a plurality of switching elements connected in parallel and disposed in the signal path, wherein each said switching element comprises a Phase Change Material (PCM) structure,
• wherein the PCM structure of each said switching structure comprises a chalcogenide glass member connected between two electrodes, wherein each of the plurality of switching structures further comprises a heater element configured to transmit heat onto said chalcogenide glass member during switching operations in response to an applied switching voltage, and
• wherein said each switching element further comprises a thermally conductive material structure disposed under said heater element and said chalcogenide glass member.

An integrated circuit (IC) switch configured to control signals transmitted along a signal path, the switch comprising:

• a plurality of Metal-Oxide-Silicon (MOS) transistors coupled in series in the signal path;
• and
• a plurality of switching elements connected in parallel and disposed in the signal path, wherein each said switching element comprises a Phase Change Material (PCM) structure,
• wherein said plurality of switching elements includes a plurality of PCM cell groups, each said PCM cell group including multiple said PCM cells connected in parallel,
• wherein each of the plurality of MOS transistors is connected to at least one of said plurality of PCM cell groups,
• wherein each of the plurality of MOS transistors is configured with a breakdown voltage that is above a first voltage level, and
• wherein each of said plurality of PCM cells is configured such that said each PCM cell is biased to conduct current when a voltage across said each PCM cell is above a second voltage level that is lower than the first voltage level.

A system including:

• an antenna;
• a transmitter circuit;
• an antenna switch circuit operably coupled between the antenna and the transmitter circuit such that, in a first operating state, said antenna switch circuit forms a low-resistance path between the transmitter circuit and the antenna, and such that, in a second operating state, said antenna switch circuit forms a high-resistance path between the transmitter circuit and the antenna, said antenna switch circuit including at least one branch comprising:
• a plurality of Metal-Oxide-Silicon (MOS) transistors respectively fabricated on associated SOI islands such that each said SOI island is separated from one or more adjacent said SOI islands by an associated intervening isolation region;
• and
• a plurality of Phase Change Material (PCM) cell groups disposed on a dielectric layer that is formed over the plurality of MOS transistors, each said PCM cell group including a plurality of PCM cells disposed on an associated region of said dielectric layer that is disposed between an associated pair said MOS transistors, wherein the plurality of PCM cells of said each PCM cell group are connected in parallel between a drain terminal of a first MOS transistor of said associated pair of MOS transistors and a source terminal of a second MOS transistor of said associated pair of MOS transistors.

An integrated circuit switch comprising:

• first and second Metal-Oxide-Silicon (MOS) transistors connected in series along a signal path;
• and
• a plurality of switching elements connected in parallel between a drain terminal of said first MOS transistor and a source terminal of said second MOS transistor,
• wherein each said switching element comprises one of a chalcogenide glass structure and a ReRAM element.