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US 9,912,323 B1Granted
Radiation hardened structured ASIC platform with compensation of delay for temperature and voltage variations for multiple redundant temporal voting latch technology
AssigneeMicro Research & Development Corporation
InventorSasan Ardalan
Life of this patent
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Abstract
The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.
Claims12
A sequential circuit for implementation in an integrated circuit device comprising:
- (a) a stable output circuit for providing a process-invariant addition-based bias current source (I), the stable output circuit comprising:
- (i) a first n-channel field effect transistor (NFET) (M1) and a second n-channel field effect transistor (NFET) (M3), each of NFET M1 and NFET M3 having the same width and length and configured in a common centroid layout wherein drain current I1 of NFET M1 and drain current I1 of NFET M3 change in the same way when voltage and/or temperature process conditions change;
- and
- (ii) a third n-channel field effect transistor (NFET) (M2) having drain current I2, wherein NFET M2 is operatively connected to NFET M1 and NFET M3;
- wherein if drain current I1 increases due to process variation, gate voltage of M2 is pulled down resulting in lower drain current I2;
- wherein if drain current I1 decreases due to process variation, gate voltage of M2 is pulled up resulting in higher drain current I2;
- and
- wherein the sum of I1 and I2 always equals output current (I);
- (b) a clock generating circuit to generate first, second, third, and fourth clock signals from a master clock signal wherein periods between the clock signals exceed a duration of a pulse width of a single event upset;
- (c) a temporally redundant latch receiving output current (I) from the stable output circuit and connected to the clock generating circuit, the temporally redundant latch comprising:
- (i) a first sampling circuit triggered by the first clock signal to sample input data at a first time;
- (ii) a second sampling circuit triggered by the second clock signal to sample the input data at a second time;
- (iii) a third sampling circuit triggered by the third clock signal to sample the input data at a third time;
- and
- (iv) a sample release circuit coupled to the first, second, and third sampling circuits and triggered by the fourth clock signal to output at a fourth time a majority of the samples collected by the first, second, and third sampling circuits;
- wherein an increase in the control voltage decreases the periods between the clock signals, and a decrease in the control voltage increases the periods between the clock signals.
13 more elements
A method for controlling upsets in an integrated circuit device, comprising:
- (1) providing a sequential circuit comprising:
- (a) a stable output circuit for providing a process-invariant addition-based bias current source (I), the stable output circuit comprising:
- (i) a first n-channel field effect transistor (NFET) (M1) and a second n-channel field effect transistor (NFET) (M3), each of NFET M1 and NFET M3 having the same width and length and configured in a common centroid layout wherein drain current I1 of NFET M1 and drain current I1 of NFET M3 change in the same way when voltage and/or temperature process conditions change;
- and
- (ii) a third n-channel field effect transistor (NFET) (M2) having drain current I2, wherein NFET M2 is operatively connected to NFET M1 and NFET M3;
- wherein if drain current I1 increases due to process variation, gate voltage of M2 is pulled down resulting in lower drain current I2;
- wherein if drain current I1 decreases due to process variation, gate voltage of M2 is pulled up resulting in higher drain current I2;
- and
- wherein the sum of I1 and I2 always equals output current (I);
- (b) a clock generating circuit to generate first, second, third, and fourth clock signals from a master clock signal wherein periods between the clock signals exceed a duration of a pulse width of a single event upset;
- (c) a temporally redundant latch receiving output current (I) from the stable output circuit and connected to the clock generating circuit, the temporally redundant latch comprising:
- (i) a first sampling circuit triggered by the first clock signal to sample input data at a first time;
- (ii) a second sampling circuit triggered by the second clock signal to sample the input data at a second time;
- (iii) a third sampling circuit triggered by the third clock signal to sample the input data at a third time;
- and
- (iv) a sample release circuit coupled to the first, second, and third sampling circuits and triggered by the fourth clock signal to output at a fourth time a majority of the samples collected by the first, second, and third sampling circuits;
- wherein an increase in the control voltage decreases the periods between the clock signals, and a decrease in the control voltage increases the periods between the clock signals;
- (2) receiving data into the sequential circuit and sampling the data at multiple different times to produce multiple time-spaced samples that are spaced temporally longer than a pulse width of a single event upset;
- (3) collecting the time-spaced samples at another time;
- and
- (4) selecting a majority from the time-spaced samples;
- wherein an increase in the control voltage decreases the periods between the different times, and a decrease in the control voltage increases the periods between the different times.
19 more elements
Dependencies are inferred from the claim text.