NAND flash memory and fabrication methods thereof

A method for fabricating an NAND flash memory, comprising:

• providing a semiconductor substrate including a core region and a peripheral region;
• forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a trench;
• forming a first dielectric layer to fill each trench;
• forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, wherein the flowable dielectric layer is graphene oxide or graphite oxide;
• performing a solidification treatment process on the flowable dielectric layer to form a solid dielectric layer, wherein voids and seams formed in a top portion of the first dielectric layer are filled by the solid dielectric layer;
• removing the solid dielectric layer and a portion of the first dielectric layer by an etch-back process to expose at least a top portion of the gate stack structures;
• forming a metal silicide layer on an exposed portion of the gate stack structures and the first dielectric layer;
• and
• removing a portion of the metal silicide layer formed on the first dielectric layer.