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US 9,911,501 B2Granted
Sensing amplifier comprising a built-in sensing offset for flash memory devices
AssigneeSilicon Storage Technology, Inc.
InventorsHieu Van Tran, Anh Ly, Thuan Vu
Life of this patent
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Abstract
The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors. In another embodiment, the sensing amplifier utilizes sloped timing for the reference signal to increase the margin by which a “0” or “1” are detected from the current drawn by the selected cell compared to the reference cell. In an another embodiment, a sensing amplifier is used without any voltage offset.
Claims49
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- a first circuit for applying a bias voltage to the selected bit line and a second circuit for applying a bias voltage to the dummy bit line;
- a first input transistor coupled to the selected bit line and a second input transistor coupled to the dummy bit line;
- and
- a built-in sensing offset generated by one or more differences in characteristics of the first input transistor and the second input transistor.
5 more elements
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- a first circuit for applying a bias voltage to the selected bit line and a second circuit for applying a bias voltage to the dummy bit line;
- a first inverter coupled to the selected bit line and a second inverter coupled to the dummy bit line;
- and
- a built-in sensing offset generated by the ratio of the first inverter and second inverter.
5 more elements
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- a first circuit for applying a bias voltage to the selected bit line and a second circuit for applying a bias voltage to the dummy bit line;
- a first input transistor coupled to the selected bit line and a second input transistor coupled to the dummy bit line;
- and
- a built-in sensing offset generated by the application of different bias currents to first input transistor and the second input transistor.
5 more elements
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- wherein the comparator comprises a first input transistor coupled to the selected bit line and a second input transistor coupled to the dummy bit line and a built-in offset is generated by one or more differences in characteristics of the first input transistor and the second input transistor.
2 more elements
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- wherein the comparator comprises a first inverter coupled to the selected bit line and a second inverter coupled to the dummy bit line, and a sensing offset is generated by the ratio of the first inverter and second inverter.
2 more elements
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- wherein the comparator comprises a first input transistor coupled to the selected bit line and a second input transistor coupled to the dummy bit line and a sensing offset is generated by the application of different bias currents to first input transistor and the second input transistor.
2 more elements
A non-volatile memory device comprising:
- a first array of flash memory cells;
- a second array of flash memory cells;
- a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising:
- a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell;
- and
- a first circuit for applying a bias voltage to the selected bit line and a second circuit for applying a bias voltage to the dummy bit line;
- wherein the comparator comprises a first input transistor coupled to the selected bit line and a second input transistor coupled to the dummy bit line and an offset voltage is generated by one or more differences in characteristics of the first input transistor and the second input transistor.
4 more elements
Dependencies are inferred from the claim text.