Overvoltage detection circuit for detecting an overvoltage spike from an external power supply

A data storage device coupled to an external power supply, the data storage device comprising:

• an overvoltage detection circuit coupled to the external power supply via a voltage supply line, the overvoltage detection circuit comprising:
• a transistor comprising a first terminal coupled to the voltage supply line, a second terminal coupled to the first terminal via a resistor, the second terminal coupled to a parasitic capacitor, the transistor configured to:
• receive an overvoltage spike on the first terminal of the transistor from the external power supply via the voltage supply line;
• and
• provide an output voltage on a third terminal of the transistor to indicate detection of the overvoltage spike when it has:
• a duration less than a time constant based on the resistor and the parasitic capacitor;
• and
• an amplitude that exceeds a threshold voltage of the transistor;
• and
• a monitor circuit configured to receive the output voltage from the transistor and provide a digital signal providing a notification of the detected overvoltage spike on the voltage supply line;
• and
• a controller coupled to non-volatile memory, the controller configured to receive the notification of the detected overvoltage spike on the voltage supply line and record its occurrence in the non-volatile memory.

A data storage device coupled to an external power supply, the data storage device comprising:

• first and second overvoltage detection circuits coupled to the external power supply via respective first and second voltage supply lines, each overvoltage detection circuit comprising:
• a transistor comprising a first terminal coupled to the respective voltage supply line, a second terminal coupled to the first terminal via a resistor, the second terminal coupled to a parasitic capacitor, the transistor configured to:
• receive an overvoltage spike on the first terminal of the transistor via the respective voltage supply line;
• and
• provide an output voltage on a third terminal of the transistor to indicate detection of the overvoltage spike when it has:
• a duration less than a time constant based on the resistor and the parasitic capacitor;
• and
• an amplitude that exceeds a threshold voltage of the transistor;
• and
• a monitor circuit configured to receive the output voltage from the transistor and provide a digital signal providing a notification of the detected overvoltage spike on the respective voltage supply line;
• and
• a controller coupled to non-volatile memory, the controller configured to receive notification of the detected overvoltage spike on the respective voltage supply line and record its occurrence in the non-volatile memory.